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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2016-04-06 16:37:20 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-04-12 13:41:44 -0700 |
| commit | e6533d36a83b81d8b5e47e0271fb8a47bf5b09a6 (patch) | |
| tree | aac0d901047ab837ab9aad5cc8b01baeb3acb849 /power | |
| parent | 80680c7ffc785eb5c4212cb7ce438b11e71042e1 (diff) | |
| download | chrome-ec-e6533d36a83b81d8b5e47e0271fb8a47bf5b09a6.tar.gz | |
chell: pmic: Delay disable of V0.85A
Various voltage rails will be enabled / disabled by the PMIC when
GPIO_PMIC_SLP_SUS_L changes. We need to delay the disable of V0.85A
by approximately 25ms in order to allow V1.00A to sufficiently discharge
first.
BUG=chrome-os-partner:52047
TEST=Probe V1.00A and V0.85A during power-down, verify V1.00A discharges
faster than V0.85A.
BRANCH=glados
Change-Id: Ibbf4f989e1814e131dc373d2b5da9b6fa1ac9cce
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337325
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/skylake.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/power/skylake.c b/power/skylake.c index 7346ad95a6..58f2d58f12 100644 --- a/power/skylake.c +++ b/power/skylake.c @@ -72,11 +72,16 @@ void chipset_force_shutdown(void) } } +__attribute__((weak)) void chipset_set_pmic_slp_sus_l(int level) +{ + gpio_set_level(GPIO_PMIC_SLP_SUS_L, level); +} + static void chipset_force_g3(void) { CPRINTS("Forcing fake G3."); - gpio_set_level(GPIO_PMIC_SLP_SUS_L, 0); + chipset_set_pmic_slp_sus_l(0); } void chipset_reset(int cold_reset) @@ -161,7 +166,7 @@ static void handle_slp_sus(enum power_state state) return; /* Always mimic PCH SLP_SUS request for all other states. */ - gpio_set_level(GPIO_PMIC_SLP_SUS_L, gpio_get_level(GPIO_PCH_SLP_SUS_L)); + chipset_set_pmic_slp_sus_l(gpio_get_level(GPIO_PCH_SLP_SUS_L)); } #ifdef CONFIG_BOARD_HAS_RTC_RESET |