power: Group Intel x86 power sequencing common code

Grouping the Intel x86 power sequencing common code so that
the future chipset power sequencing implementation can make
use of the existing code.

BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
     Manually tested on Reef & Chell.
     System can boot to OS. S3, S5, hibernate are working.

Change-Id: I29dc208eacb3db47c640d028e9551ab3d8d4288c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/402272
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

6 files changed, 301 insertions, 530 deletions

diff --git a/power/apollolake.c b/power/apollolake.c
index adb93f3256..43e4360ba2 100644
--- a/power/apollolake.c
+++ b/power/apollolake.c
@@ -6,49 +6,15 @@
 /* Apollolake chipset power control module for Chrome EC */
 
 #include "apollolake.h"
-#include "charge_state.h"
-#include "chipset.h"
 #include "console.h"
-#include "ec_commands.h"
-#include "hooks.h"
+#include "gpio.h"
 #include "intel_x86.h"
-#include "lpc.h"
-#include "system.h"
-#include "util.h"
-#include "wireless.h"
+#include "timer.h"
 
 /* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
 #define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
 
 static int forcing_coldreset; /* Forced coldreset in progress? */
-static int power_s5_up;       /* Chipset is sequencing up or down */
-
-enum sys_sleep_state {
-	SYS_SLEEP_S5,
-	SYS_SLEEP_S4,
-	SYS_SLEEP_S3
-};
-
-/* Get system sleep state through GPIOs or VWs */
-static int chipset_get_sleep_signal(enum sys_sleep_state state)
-{
-#ifdef CONFIG_ESPI_VW_SIGNALS
-	if (state == SYS_SLEEP_S4)
-		return espi_vw_get_wire(VW_SLP_S4_L);
-	else if (state == SYS_SLEEP_S3)
-		return espi_vw_get_wire(VW_SLP_S3_L);
-#else
-	if (state == SYS_SLEEP_S4)
-		return gpio_get_level(GPIO_PCH_SLP_S4_L);
-	else if (state == SYS_SLEEP_S3)
-		return gpio_get_level(GPIO_PCH_SLP_S3_L);
-#endif
-
-	/* We should never run here */
-	ASSERT(0);
-	return 0;
-}
 
 __attribute__((weak)) void chipset_do_shutdown(void)
 {
@@ -63,9 +29,17 @@ void chipset_force_shutdown(void)
 	chipset_do_shutdown();
 }
 
-void chipset_force_g3(void)
+enum power_state chipset_force_g3(void)
 {
 	chipset_force_shutdown();
+
+	/* Power up the platform again for forced cold reset */
+	if (forcing_coldreset) {
+		forcing_coldreset = 0;
+		return POWER_G3S5;
+	}
+
+	return POWER_G3;
 }
 
 void chipset_reset(int cold_reset)
@@ -129,248 +103,28 @@ static void handle_all_sys_pgood(enum power_state state)
 	CPRINTS("Pass through GPIO_ALL_SYS_PGOOD: %d", in_level);
 }
 
-static enum power_state _power_handle_state(enum power_state state)
+enum power_state power_handle_state(enum power_state state)
 {
-	int tries = 0;
-
-	switch (state) {
-	case POWER_G3:
-		break;
-
-	case POWER_S5:
-#ifdef CONFIG_BOARD_HAS_RTC_RESET
-		/* Wait for S5 exit and attempt RTC reset it supported */
-		if (power_s5_up)
-			return power_wait_s5_rtc_reset();
-#endif
-
-		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			/* Required rail went away */
-			chipset_force_shutdown();
-			return POWER_S5G3;
-		} else if (chipset_get_sleep_signal(SYS_SLEEP_S4) == 1) {
-			/* Power up to next state */
-			return POWER_S5S3;
-		}
-		break;
-
-	case POWER_S3:
-		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			/* Required rail went away */
-			chipset_force_shutdown();
-			return POWER_S3S5;
-		} else if (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1) {
-			/* Power up to next state */
-			return POWER_S3S0;
-		} else if (chipset_get_sleep_signal(SYS_SLEEP_S4) == 0) {
-			/* Power down to next state */
-			return POWER_S3S5;
-		}
-		break;
-
-	case POWER_S0:
-		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			chipset_force_shutdown();
-			return POWER_S0S3;
-#ifdef CONFIG_POWER_S0IX
-		} else if ((power_get_host_sleep_state() ==
-			    HOST_SLEEP_EVENT_S0IX_SUSPEND) &&
-			   (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) {
-			return POWER_S0S0ix;
-#endif
-		} else if (chipset_get_sleep_signal(SYS_SLEEP_S3) == 0) {
-			/* Power down to next state */
-			return POWER_S0S3;
-		}
+	enum power_state new_state;
 
-		break;
+	/* Process ALL_SYS_PGOOD state changes. */
+	handle_all_sys_pgood(state);
 
-#ifdef CONFIG_POWER_S0IX
-	case POWER_S0ix:
-		/*
-		 * TODO: add code for unexpected power loss
-		 */
-		if ((power_get_host_sleep_state() ==
-		     HOST_SLEEP_EVENT_S0IX_RESUME) &&
-		   (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) {
-			return POWER_S0ixS0;
-		}
+	if (state == POWER_S5 && !power_has_signals(IN_PGOOD_ALL_CORE)) {
+		/* Required rail went away */
+		chipset_force_shutdown();
 
-		break;
-#endif
+		new_state = POWER_S5G3;
+		goto rsmrst_handle;
 
-	case POWER_G3S5:
+	} else if (state == POWER_G3S5) {
 		/* Platform is powering up, clear forcing_coldreset */
 		forcing_coldreset = 0;
-
-		/*
-		 * Allow up to 1s for charger to be initialized, in case
-		 * we're trying to boot the AP with no battery.
-		 */
-		while (charge_prevent_power_on(0) &&
-		       tries++ < CHARGER_INITIALIZED_TRIES) {
-			msleep(CHARGER_INITIALIZED_DELAY_MS);
-		}
-
-		/* Return to G3 if battery level is too low */
-		if (charge_want_shutdown() ||
-		    tries > CHARGER_INITIALIZED_TRIES) {
-			CPRINTS("power-up inhibited");
-			chipset_force_shutdown();
-			return POWER_G3;
-		}
-
-		/* Call hooks to initialize PMIC */
-		hook_notify(HOOK_CHIPSET_PRE_INIT);
-
-		/* Wait for RSMRST_L de-assert */
-		if (power_wait_signals(IN_PGOOD_ALL_CORE)) {
-			chipset_force_shutdown();
-			return POWER_G3;
-		}
-
-		power_s5_up = 1;
-		return POWER_S5;
-
-	case POWER_S5S3:
-		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			/* Required rail went away */
-			chipset_force_shutdown();
-			return POWER_S5G3;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-
-#ifdef CONFIG_POWER_S0IX
-		/*
-		 * Clearing the S0ix flag on the path to S0
-		 * to handle any reset conditions.
-		 */
-		power_reset_host_sleep_state(HOST_SLEEP_EVENT_S0IX_RESUME);
-#endif
-		return POWER_S3;
-
-	case POWER_S3S0:
-		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			/* Required rail went away */
-			chipset_force_shutdown();
-			return POWER_S3S5;
-		}
-
-		gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-
-		/* Enable wireless */
-		wireless_set_state(WIRELESS_ON);
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * Throttle CPU if necessary.  This should only be asserted
-		 * when +VCCP is powered (it is by now).
-		 */
-		gpio_set_level(GPIO_CPU_PROCHOT, 0);
-
-		return POWER_S0;
-
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-		gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-
-		/* Suspend wireless */
-		wireless_set_state(WIRELESS_SUSPEND);
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-#ifdef CONFIG_POWER_S0IX
-		/* re-init S0ix flag */
-		power_reset_host_sleep_state(HOST_SLEEP_EVENT_S0IX_RESUME);
-#endif
-		return POWER_S3;
-
-#ifdef CONFIG_POWER_S0IX
-	case POWER_S0S0ix:
-		/* call hooks before standby */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-		lpc_enable_wake_mask_for_lid_open();
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S0ix.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-		return POWER_S0ix;
-
-
-	case POWER_S0ixS0:
-		lpc_disable_wake_mask_for_lid_open();
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		return POWER_S0;
-#endif
-
-	case POWER_S3S5:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		/* Disable wireless */
-		wireless_set_state(WIRELESS_OFF);
-
-		/* Always enter into S5 state. The S5 state is required to
-		 * correctly handle global resets which have a bit of delay
-		 * while the SLP_Sx_L signals are asserted then deasserted. */
-		power_s5_up = 0;
-		return POWER_S5;
-
-	case POWER_S5G3:
-		chipset_force_shutdown();
-
-		/* Power up the platform again for forced cold reset */
-		if (forcing_coldreset) {
-			forcing_coldreset = 0;
-			return POWER_G3S5;
-		}
-
-		return POWER_G3;
-
-	default:
-		break;
 	}
 
-	return state;
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	enum power_state new_state;
-
-	/* Process ALL_SYS_PGOOD state changes. */
-	handle_all_sys_pgood(state);
+	new_state = common_intel_x86_power_handle_state(state);
 
-	new_state = _power_handle_state(state);
+rsmrst_handle:
 
 	/*
 	 * Process RSMRST_L state changes:
diff --git a/power/apollolake.h b/power/apollolake.h
index 424da3cefc..78aad94b5a 100644
--- a/power/apollolake.h
+++ b/power/apollolake.h
@@ -26,6 +26,8 @@
 
 #define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
 
+#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PGOOD_ALL_CORE
+
 #define CHARGER_INITIALIZED_DELAY_MS 100
 #define CHARGER_INITIALIZED_TRIES 40
 
diff --git a/power/intel_x86.c b/power/intel_x86.c
index 616ee739a9..4932d4e655 100644
--- a/power/intel_x86.c
+++ b/power/intel_x86.c
@@ -5,12 +5,21 @@
 
 /* Intel X86 chipset power control module for Chrome EC */
 
+#include "charge_state.h"
 #include "chipset.h"
 #include "console.h"
+#include "ec_commands.h"
+#include "espi.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "intel_x86.h"
+#include "lpc.h"
+#include "power.h"
+#include "power_button.h"
 #include "system.h"
 #include "task.h"
+#include "util.h"
+#include "wireless.h"
 
 /* Chipset specific header files */
 #ifdef CONFIG_CHIPSET_APOLLOLAKE
@@ -22,8 +31,36 @@
 /* Console output macros */
 #define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
 
+enum sys_sleep_state {
+	SYS_SLEEP_S5,
+	SYS_SLEEP_S4,
+	SYS_SLEEP_S3
+};
+
+int power_s5_up;       /* Chipset is sequencing up or down */
+
+/* Get system sleep state through GPIOs or VWs */
+static int chipset_get_sleep_signal(enum sys_sleep_state state)
+{
+#ifdef CONFIG_ESPI_VW_SIGNALS
+	if (state == SYS_SLEEP_S4)
+		return espi_vw_get_wire(VW_SLP_S4_L);
+	else if (state == SYS_SLEEP_S3)
+		return espi_vw_get_wire(VW_SLP_S3_L);
+#else
+	if (state == SYS_SLEEP_S4)
+		return gpio_get_level(GPIO_PCH_SLP_S4_L);
+	else if (state == SYS_SLEEP_S3)
+		return gpio_get_level(GPIO_PCH_SLP_S3_L);
+#endif
+
+	/* We should never run here */
+	ASSERT(0);
+	return 0;
+}
+
 #ifdef CONFIG_BOARD_HAS_RTC_RESET
-enum power_state power_wait_s5_rtc_reset(void)
+static enum power_state power_wait_s5_rtc_reset(void)
 {
 	static int s5_exit_tries;
 
@@ -80,3 +117,220 @@ enum power_state power_chipset_init(void)
 
 	return POWER_G3;
 }
+
+enum power_state common_intel_x86_power_handle_state(enum power_state state)
+{
+	int tries = 0;
+
+	switch (state) {
+	case POWER_G3:
+		break;
+
+	case POWER_S5:
+#ifdef CONFIG_BOARD_HAS_RTC_RESET
+		/* Wait for S5 exit and attempt RTC reset it supported */
+		if (power_s5_up)
+			return power_wait_s5_rtc_reset();
+#endif
+
+		if (chipset_get_sleep_signal(SYS_SLEEP_S4) == 1)
+			return POWER_S5S3; /* Power up to next state */
+		break;
+
+	case POWER_S3:
+		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
+			/* Required rail went away */
+			chipset_force_shutdown();
+			return POWER_S3S5;
+		} else if (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1) {
+			/* Power up to next state */
+			return POWER_S3S0;
+		} else if (chipset_get_sleep_signal(SYS_SLEEP_S4) == 0) {
+			/* Power down to next state */
+			return POWER_S3S5;
+		}
+		break;
+
+	case POWER_S0:
+		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
+			chipset_force_shutdown();
+			return POWER_S0S3;
+		} else if (chipset_get_sleep_signal(SYS_SLEEP_S3) == 0) {
+			/* Power down to next state */
+			return POWER_S0S3;
+#ifdef CONFIG_POWER_S0IX
+		} else if (power_get_host_sleep_state() ==
+			    HOST_SLEEP_EVENT_S0IX_SUSPEND) {
+			return POWER_S0S0ix;
+#endif
+		}
+
+		break;
+
+#ifdef CONFIG_POWER_S0IX
+	case POWER_S0ix:
+		/*
+		 * TODO: crosbug.com/p/61645
+		 * Add code to handle unexpected power loss.
+		 */
+		if ((power_get_host_sleep_state() ==
+		     HOST_SLEEP_EVENT_S0IX_RESUME) &&
+		   (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) {
+			return POWER_S0ixS0;
+		}
+
+		break;
+#endif
+
+	case POWER_G3S5:
+		/*
+		 * Allow charger to be initialized for upto defined tries,
+		 * in case we're trying to boot the AP with no battery.
+		 */
+		while (charge_prevent_power_on(0) &&
+		       tries++ < CHARGER_INITIALIZED_TRIES) {
+			msleep(CHARGER_INITIALIZED_DELAY_MS);
+		}
+
+		/* Return to G3 if battery level is too low */
+		if (charge_want_shutdown() ||
+		    tries > CHARGER_INITIALIZED_TRIES) {
+			CPRINTS("power-up inhibited");
+			chipset_force_shutdown();
+			return POWER_G3;
+		}
+
+		/* Call hooks to initialize PMIC */
+		hook_notify(HOOK_CHIPSET_PRE_INIT);
+
+		if (power_wait_signals(CHIPSET_G3S5_POWERUP_SIGNAL)) {
+			chipset_force_shutdown();
+			return POWER_G3;
+		}
+
+		power_s5_up = 1;
+		return POWER_S5;
+
+	case POWER_S5S3:
+		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
+			/* Required rail went away */
+			chipset_force_shutdown();
+			return POWER_S5G3;
+		}
+
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_STARTUP);
+
+#ifdef CONFIG_POWER_S0IX
+		/*
+		 * Clearing the S0ix flag on the path to S0
+		 * to handle any reset conditions.
+		 */
+		power_reset_host_sleep_state(HOST_SLEEP_EVENT_S0IX_RESUME);
+#endif
+		return POWER_S3;
+
+	case POWER_S3S0:
+		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
+			/* Required rail went away */
+			chipset_force_shutdown();
+			return POWER_S3S5;
+		}
+
+		gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
+
+		/* Enable wireless */
+		wireless_set_state(WIRELESS_ON);
+
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_RESUME);
+
+		/*
+		 * Disable idle task deep sleep. This means that the low
+		 * power idle task will not go into deep sleep while in S0.
+		 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+
+		/*
+		 * Throttle CPU if necessary.  This should only be asserted
+		 * when +VCCP is powered (it is by now).
+		 */
+		gpio_set_level(GPIO_CPU_PROCHOT, 0);
+
+		return POWER_S0;
+
+	case POWER_S0S3:
+		/* Call hooks before we remove power rails */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+
+		gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
+
+		/* Suspend wireless */
+		wireless_set_state(WIRELESS_SUSPEND);
+
+		/*
+		 * Enable idle task deep sleep. Allow the low power idle task
+		 * to go into deep sleep in S3 or lower.
+		 */
+		enable_sleep(SLEEP_MASK_AP_RUN);
+
+#ifdef CONFIG_POWER_S0IX
+		/* re-init S0ix flag */
+		power_reset_host_sleep_state(HOST_SLEEP_EVENT_S0IX_RESUME);
+#endif
+		return POWER_S3;
+
+#ifdef CONFIG_POWER_S0IX
+	case POWER_S0S0ix:
+		/* call hooks before standby */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+
+		lpc_enable_wake_mask_for_lid_open();
+
+		/*
+		 * Enable idle task deep sleep. Allow the low power idle task
+		 * to go into deep sleep in S0ix.
+		 */
+		enable_sleep(SLEEP_MASK_AP_RUN);
+
+		return POWER_S0ix;
+
+
+	case POWER_S0ixS0:
+		lpc_disable_wake_mask_for_lid_open();
+
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_RESUME);
+
+		/*
+		 * Disable idle task deep sleep. This means that the low
+		 * power idle task will not go into deep sleep while in S0.
+		 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+
+		return POWER_S0;
+#endif
+
+	case POWER_S3S5:
+		/* Call hooks before we remove power rails */
+		hook_notify(HOOK_CHIPSET_SHUTDOWN);
+
+		/* Disable wireless */
+		wireless_set_state(WIRELESS_OFF);
+
+		/* Always enter into S5 state. The S5 state is required to
+		 * correctly handle global resets which have a bit of delay
+		 * while the SLP_Sx_L signals are asserted then deasserted.
+		 */
+		power_s5_up = 0;
+		return POWER_S5;
+
+	case POWER_S5G3:
+		return chipset_force_g3();
+
+	default:
+		break;
+	}
+
+	return state;
+}
diff --git a/power/intel_x86.h b/power/intel_x86.h
index 08d9b89a6f..614f0197b1 100644
--- a/power/intel_x86.h
+++ b/power/intel_x86.h
@@ -11,6 +11,8 @@
 
 #include "power.h"
 
+extern int power_s5_up;       /* Chipset is sequencing up or down */
+
 /**
  * Handle RSMRST signal.
  *
@@ -20,14 +22,17 @@ void handle_rsmrst(enum power_state state);
 
 /**
  * Force chipset to G3 state.
+ *
+ * @return power_state New chipset state.
  */
-void chipset_force_g3(void);
+enum power_state chipset_force_g3(void);
 
 /**
- * Wait for S5 exit and then attempt RTC reset.
+ * Handle power states.
  *
+ * @param state        Current chipset state.
  * @return power_state New chipset state.
  */
-enum power_state power_wait_s5_rtc_reset(void);
+enum power_state common_intel_x86_power_handle_state(enum power_state state);
 
 #endif /* __CROS_EC_INTEL_X86_H */
diff --git a/power/skylake.c b/power/skylake.c
index 1bdad6d491..c821ecb268 100644
--- a/power/skylake.c
+++ b/power/skylake.c
@@ -6,52 +6,20 @@
 /* Skylake IMVP8 / ROP PMIC chipset power control module for Chrome EC */
 
 #include "board_config.h"
-#include "charge_state.h"
 #include "chipset.h"
 #include "console.h"
-#include "ec_commands.h"
-#include "espi.h"
-#include "hooks.h"
+#include "gpio.h"
 #include "intel_x86.h"
 #include "lpc.h"
 #include "power_button.h"
 #include "skylake.h"
-#include "system.h"
-#include "util.h"
-#include "wireless.h"
+#include "timer.h"
 
 /* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
 #define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
 
 static int forcing_shutdown;  /* Forced shutdown in progress? */
-static int power_s5_up;       /* Chipset is sequencing up or down */
 
-enum sys_sleep_state {
-	SYS_SLEEP_S5,
-	SYS_SLEEP_S4,
-	SYS_SLEEP_S3
-};
-
-/* Get system sleep state through GPIOs or VWs */
-static int chipset_get_sleep_signal(enum sys_sleep_state state)
-{
-#ifdef CONFIG_ESPI_VW_SIGNALS
-	if (state == SYS_SLEEP_S4)
-		return espi_vw_get_wire(VW_SLP_S4_L);
-	else if (state == SYS_SLEEP_S3)
-		return espi_vw_get_wire(VW_SLP_S3_L);
-#else
-	if (state == SYS_SLEEP_S4)
-		return gpio_get_level(GPIO_PCH_SLP_S4_L);
-	else if (state == SYS_SLEEP_S3)
-		return gpio_get_level(GPIO_PCH_SLP_S3_L);
-#endif
-
-	/* We should never run here */
-	ASSERT(0);
-	return 0;
-}
 
 void chipset_force_shutdown(void)
 {
@@ -75,11 +43,13 @@ __attribute__((weak)) void chipset_set_pmic_slp_sus_l(int level)
 	gpio_set_level(GPIO_PMIC_SLP_SUS_L, level);
 }
 
-void chipset_force_g3(void)
+enum power_state chipset_force_g3(void)
 {
 	CPRINTS("Forcing fake G3.");
 
 	chipset_set_pmic_slp_sus_l(0);
+
+	return POWER_G3;
 }
 
 void chipset_reset(int cold_reset)
@@ -148,227 +118,6 @@ static void handle_slp_sus(enum power_state state)
 	chipset_set_pmic_slp_sus_l(gpio_get_level(GPIO_PCH_SLP_SUS_L));
 }
 
-static enum power_state _power_handle_state(enum power_state state)
-{
-	int tries = 0;
-
-	switch (state) {
-	case POWER_G3:
-		break;
-
-	case POWER_S5:
-		if (forcing_shutdown) {
-			power_button_pch_release();
-			forcing_shutdown = 0;
-		}
-
-#ifdef CONFIG_BOARD_HAS_RTC_RESET
-		/* Wait for S5 exit and attempt RTC reset it supported */
-		if (power_s5_up)
-			return power_wait_s5_rtc_reset();
-#endif
-		if (chipset_get_sleep_signal(SYS_SLEEP_S4) == 1)
-			return POWER_S5S3; /* Power up to next state */
-		break;
-
-	case POWER_S3:
-		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			/* Required rail went away */
-			chipset_force_shutdown();
-			return POWER_S3S5;
-		} else if (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1) {
-			/* Power up to next state */
-			return POWER_S3S0;
-		} else if (chipset_get_sleep_signal(SYS_SLEEP_S4) == 0) {
-			/* Power down to next state */
-			return POWER_S3S5;
-		}
-		break;
-
-	case POWER_S0:
-		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			chipset_force_shutdown();
-			return POWER_S0S3;
-#ifdef CONFIG_POWER_S0IX
-		} else if ((power_get_host_sleep_state() ==
-			    HOST_SLEEP_EVENT_S0IX_SUSPEND) &&
-			   (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) {
-			return POWER_S0S0ix;
-#endif
-		} else if (chipset_get_sleep_signal(SYS_SLEEP_S3) == 0) {
-			/* Power down to next state */
-			return POWER_S0S3;
-		}
-
-		break;
-
-#ifdef CONFIG_POWER_S0IX
-	case POWER_S0ix:
-		/*
-		 * TODO: add code for unexpected power loss
-		 */
-		if ((power_get_host_sleep_state() ==
-		     HOST_SLEEP_EVENT_S0IX_RESUME) &&
-		   (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) {
-			return POWER_S0ixS0;
-		}
-
-		break;
-#endif
-
-	case POWER_G3S5:
-		/* Call hooks to initialize PMIC */
-		hook_notify(HOOK_CHIPSET_PRE_INIT);
-
-		/*
-		 * Allow up to 1s for charger to be initialized, in case
-		 * we're trying to boot the AP with no battery.
-		 */
-		while (charge_prevent_power_on(0) &&
-		       tries++ < CHARGER_INITIALIZED_TRIES) {
-			msleep(CHARGER_INITIALIZED_DELAY_MS);
-		}
-
-		/* Return to G3 if battery level is too low */
-		if (charge_want_shutdown() ||
-		    tries > CHARGER_INITIALIZED_TRIES) {
-			CPRINTS("power-up inhibited");
-			chipset_force_shutdown();
-			return POWER_G3;
-		}
-
-		if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) {
-			chipset_force_shutdown();
-			return POWER_G3;
-		}
-
-		power_s5_up = 1;
-		return POWER_S5;
-
-	case POWER_S5S3:
-		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			/* Required rail went away */
-			chipset_force_shutdown();
-			return POWER_S5G3;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-
-#ifdef CONFIG_POWER_S0IX
-		/*
-		 * Clearing the S0ix flag on the path to S0
-		 * to handle any reset conditions.
-		 */
-		power_reset_host_sleep_state(HOST_SLEEP_EVENT_S0IX_RESUME);
-#endif
-		return POWER_S3;
-
-	case POWER_S3S0:
-		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			/* Required rail went away */
-			chipset_force_shutdown();
-			return POWER_S3S5;
-		}
-
-		gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-
-		/* Enable wireless */
-		wireless_set_state(WIRELESS_ON);
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * Throttle CPU if necessary.  This should only be asserted
-		 * when +VCCP is powered (it is by now).
-		 */
-		gpio_set_level(GPIO_CPU_PROCHOT, 0);
-
-		return POWER_S0;
-
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-		gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-
-		/* Suspend wireless */
-		wireless_set_state(WIRELESS_SUSPEND);
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-#ifdef CONFIG_POWER_S0IX
-		/* re-init S0ix flag */
-		power_reset_host_sleep_state(HOST_SLEEP_EVENT_S0IX_RESUME);
-#endif
-		return POWER_S3;
-
-#ifdef CONFIG_POWER_S0IX
-	case POWER_S0S0ix:
-		/* call hooks before standby */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-		lpc_enable_wake_mask_for_lid_open();
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S0ix.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-		return POWER_S0ix;
-
-
-	case POWER_S0ixS0:
-		lpc_disable_wake_mask_for_lid_open();
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		return POWER_S0;
-#endif
-
-	case POWER_S3S5:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		/* Disable wireless */
-		wireless_set_state(WIRELESS_OFF);
-
-		/* Always enter into S5 state. The S5 state is required to
-		 * correctly handle global resets which have a bit of delay
-		 * while the SLP_Sx_L signals are asserted then deasserted. */
-		power_s5_up = 0;
-		return POWER_S5;
-
-	case POWER_S5G3:
-		chipset_force_g3();
-		return POWER_G3;
-
-	default:
-		break;
-	}
-
-	return state;
-}
-
 enum power_state power_handle_state(enum power_state state)
 {
 	enum power_state new_state;
@@ -376,7 +125,12 @@ enum power_state power_handle_state(enum power_state state)
 	/* Process RSMRST_L state changes. */
 	handle_rsmrst(state);
 
-	new_state = _power_handle_state(state);
+	if (state == POWER_S5 && forcing_shutdown) {
+		power_button_pch_release();
+		forcing_shutdown = 0;
+	}
+
+	new_state = common_intel_x86_power_handle_state(state);
 
 	/* Process SLP_SUS_L state changes after a new state is decided. */
 	handle_slp_sus(new_state);
diff --git a/power/skylake.h b/power/skylake.h
index d44fb00e19..2a6f8fc4e7 100644
--- a/power/skylake.h
+++ b/power/skylake.h
@@ -28,6 +28,8 @@
 
 #define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
 
+#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
+
 #define CHARGER_INITIALIZED_DELAY_MS 100
 #define CHARGER_INITIALIZED_TRIES 40