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| author | Kattamuri, Sowjanya <sowjanya.kattamuri@intel.com> | 2020-04-02 14:58:01 +0530 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-04-08 22:23:06 +0000 |
| commit | 581e6f9a83d468d02f40c2c0d811fc25c73be54b (patch) | |
| tree | ca5d674cd254cc373dcb34bcf84a60ad8045f9f3 /power | |
| parent | f327ba4fcf20a314bba988b7aac778bbaf94101c (diff) | |
| download | chrome-ec-581e6f9a83d468d02f40c2c0d811fc25c73be54b.tar.gz | |
Power_x86: Correct the debounce delay for SYS_RESET_L signal
RVP uses MAX6818 to digitize the apreset physical button.
The EC SYS_RESET_L is connected to input of the digitizer.
From MAX6818 Data sheet, range of 'Debounce Duration' is
Minimum - 20 ms, Typical - 40 ms, Maximum - 80 ms.
Hence, implemented an override function to wait for an appropriate delay.
BUG=b:153128296
BRANCH=none
TEST=manually tested on TGLRVP, aprset EC console command triggers
warm boot
Change-Id: I4f883c925a82d32bfaaeed8120671869d3744843
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2134326
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/intel_x86.c | 15 | ||||
| -rw-r--r-- | power/intel_x86.h | 9 |
2 files changed, 19 insertions, 5 deletions
diff --git a/power/intel_x86.c b/power/intel_x86.c index 290b16c885..d1f0b17d84 100644 --- a/power/intel_x86.c +++ b/power/intel_x86.c @@ -683,6 +683,15 @@ __override void power_chipset_handle_host_sleep_event( #endif +__overridable void intel_x86_sys_reset_delay(void) +{ + /* + * Debounce time for SYS_RESET_L is 16 ms. Wait twice that period + * to be safe. + */ + udelay(32 * MSEC); +} + void chipset_reset(enum chipset_reset_reason reason) { /* @@ -708,11 +717,7 @@ void chipset_reset(enum chipset_reset_reason reason) report_ap_reset(reason); gpio_set_level(GPIO_SYS_RESET_L, 0); - /* - * Debounce time for SYS_RESET_L is 16 ms. Wait twice that period - * to be safe. - */ - udelay(32 * MSEC); + intel_x86_sys_reset_delay(); gpio_set_level(GPIO_SYS_RESET_L, 1); } diff --git a/power/intel_x86.h b/power/intel_x86.h index 52accead32..d50d6a75da 100644 --- a/power/intel_x86.h +++ b/power/intel_x86.h @@ -91,4 +91,13 @@ __override_proto int intel_x86_get_pg_ec_dsw_pwrok(void); */ __override_proto int intel_x86_get_pg_ec_all_sys_pwrgd(void); +/** + * Introduces SYS_RESET_L Debounce time delay + * + * The default implementation is to wait for a duration of 32 ms. + * If board needs a different debounce time delay, they may override + * this function + */ +__override_proto void intel_x86_sys_reset_delay(void); + #endif /* __CROS_EC_INTEL_X86_H */ |