Code cleanup: Remove cold reset logic

Majority of the chipsets do not have a dedicated GPIO to trigger
AP cold reset. Current code either ignores cold reset or does a warm
reset instead or have a work around to put AP in S5 and then bring
back to S0. In order to avoid the confusion, removed the cold reset
logic and only apreset is used hence forth.

BUG=b:72426192
BRANCH=none
TEST=make buildall -j
     Manually tested on GLKRVP, apreset EC command can reset AP.

Change-Id: Ie32d34f2f327ff1b61b32a4d874250dce024cf35
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/991052
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>

6 files changed, 37 insertions, 85 deletions

diff --git a/power/braswell.c b/power/braswell.c
index bfdf3dec39..0b91040cbc 100644
--- a/power/braswell.c
+++ b/power/braswell.c
@@ -68,38 +68,19 @@ void chipset_force_shutdown(void)
 	forcing_shutdown = 1;
 }
 
-void chipset_reset(int cold_reset)
+void chipset_reset(void)
 {
-	CPRINTS("%s(%d)", __func__, cold_reset);
-	if (cold_reset) {
-		/*
-		 * Drop and restore PWROK.  This causes the PCH to reboot,
-		 * regardless of its after-G3 setting.  This type of reboot
-		 * causes the PCH to assert PLTRST#, SLP_S3#, and SLP_S5#, so
-		 * we actually drop power to the rest of the system (hence, a
-		 * "cold" reboot).
-		 */
-
-		/* Ignore if PWROK is already low */
-		if (gpio_get_level(GPIO_PCH_SYS_PWROK) == 0)
-			return;
-
-		/* PWROK must deassert for at least 3 RTC clocks = 91 us */
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-		udelay(100);
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
+	CPRINTS("%s", __func__);
 
-	} else {
-		/*
-		 * Send a reset pulse to the PCH.  This just causes it to
-		 * assert INIT# to the CPU without dropping power or asserting
-		 * PLTRST# to reset the rest of the system.  The PCH uses a 16
-		 * ms debounce time, so assert the signal for twice that.
-		 */
-		gpio_set_level(GPIO_PCH_RCIN_L, 0);
-		usleep(32 * MSEC);
-		gpio_set_level(GPIO_PCH_RCIN_L, 1);
-	}
+	/*
+	 * Send a reset pulse to the PCH.  This just causes it to
+	 * assert INIT# to the CPU without dropping power or asserting
+	 * PLTRST# to reset the rest of the system.  The PCH uses a 16
+	 * ms debounce time, so assert the signal for twice that.
+	 */
+	gpio_set_level(GPIO_PCH_RCIN_L, 0);
+	usleep(32 * MSEC);
+	gpio_set_level(GPIO_PCH_RCIN_L, 1);
 }
 
 void chipset_throttle_cpu(int throttle)
diff --git a/power/intel_x86.c b/power/intel_x86.c
index 73cac45613..bc58d26711 100644
--- a/power/intel_x86.c
+++ b/power/intel_x86.c
@@ -510,7 +510,7 @@ void power_chipset_handle_host_sleep_event(enum host_sleep_event state)
 
 #endif
 
-void chipset_reset(int cold_reset)
+void chipset_reset(void)
 {
 	/*
 	 * Irrespective of cold_reset value, always toggle SYS_RESET_L to
diff --git a/power/mediatek.c b/power/mediatek.c
index 7ac9143803..e5bfe37e66 100644
--- a/power/mediatek.c
+++ b/power/mediatek.c
@@ -418,7 +418,7 @@ enum power_state power_chipset_init(void)
 		 * The warm reset triggers AP into the recovery mode (
 		 * flash SPI from USB).
 		 */
-		chipset_reset(0);
+		chipset_reset();
 
 		init_power_state = POWER_G3;
 	} else {
@@ -638,23 +638,13 @@ static void power_on(void)
 	CPRINTS("AP running ...");
 }
 
-void chipset_reset(int is_cold)
+void chipset_reset(void)
 {
-	if (is_cold) {
-		CPRINTS("EC triggered cold reboot");
-		set_system_power(0);
-		usleep(PMIC_COLD_RESET_L_HOLD_TIME);
-		/* Press the PMIC power button */
-		set_pmic_pwron(1);
-		hook_call_deferred(&release_pmic_pwron_deferred_data,
-				   PMIC_PWRON_PRESS_TIME);
-	} else {
-		CPRINTS("EC triggered warm reboot");
-		set_warm_reset(1);
-		usleep(PMIC_WARM_RESET_H_HOLD_TIME);
-		/* deassert the reset signals */
-		set_warm_reset(0);
-	}
+	CPRINTS("EC triggered warm reboot");
+	set_warm_reset(1);
+	usleep(PMIC_WARM_RESET_H_HOLD_TIME);
+	/* deassert the reset signals */
+	set_warm_reset(0);
 }
 
 enum power_state power_handle_state(enum power_state state)
diff --git a/power/rk3399.c b/power/rk3399.c
index 51211d0c69..2c8a5e9e96 100644
--- a/power/rk3399.c
+++ b/power/rk3399.c
@@ -220,14 +220,13 @@ void chipset_force_shutdown(void)
 }
 
 #define SYS_RST_HOLD_US (1 * MSEC)
-void chipset_reset(int cold_reset)
+void chipset_reset(void)
 {
 #ifdef CONFIG_CMD_RTC
 	/* Print out the RTC to help correlate resets in logs. */
 	print_system_rtc(CC_CHIPSET);
 #endif
-	/* TODO: handle cold_reset */
-	CPRINTS("%s(%d)", __func__, cold_reset);
+	CPRINTS("%s", __func__);
 
 	/* Pulse SYS_RST */
 	gpio_set_level(GPIO_SYS_RST_L, 0);
diff --git a/power/rockchip.c b/power/rockchip.c
index eb33d3e91e..22ec8eff5b 100644
--- a/power/rockchip.c
+++ b/power/rockchip.c
@@ -223,7 +223,7 @@ enum power_state power_chipset_init(void)
 		 * The warm reset triggers AP into the RK recovery mode (
 		 * flash SPI from USB).
 		 */
-		chipset_reset(0);
+		chipset_reset();
 
 		init_power_state = POWER_G3;
 	} else {
@@ -380,23 +380,14 @@ static void power_off(void)
 	CPRINTS("power shutdown complete");
 }
 
-void chipset_reset(int is_cold)
+void chipset_reset(void)
 {
-	if (is_cold) {
-		CPRINTS("EC triggered cold reboot");
-		power_off();
-		/* After POWER_GOOD is dropped off,
-		 * the system will be on again
-		 */
-		power_request = POWER_REQ_ON;
-	} else {
-		CPRINTS("EC triggered warm reboot");
-		CPRINTS("assert GPIO_PMIC_WARM_RESET_L for %d ms",
-				PMIC_WARM_RESET_L_HOLD_TIME / MSEC);
-		set_pmic_warm_reset(1);
-		usleep(PMIC_WARM_RESET_L_HOLD_TIME);
-		set_pmic_warm_reset(0);
-	}
+	CPRINTS("EC triggered warm reboot");
+	CPRINTS("assert GPIO_PMIC_WARM_RESET_L for %d ms",
+			PMIC_WARM_RESET_L_HOLD_TIME / MSEC);
+	set_pmic_warm_reset(1);
+	usleep(PMIC_WARM_RESET_L_HOLD_TIME);
+	set_pmic_warm_reset(0);
 }
 
 enum power_state power_handle_state(enum power_state state)
diff --git a/power/stoney.c b/power/stoney.c
index 936ae21a65..a3c6467dd7 100644
--- a/power/stoney.c
+++ b/power/stoney.c
@@ -52,30 +52,21 @@ static void chipset_force_g3(void)
 #endif
 }
 
-void chipset_reset(int cold_reset)
+void chipset_reset(void)
 {
-	CPRINTS("%s(%d)", __func__, cold_reset);
+	CPRINTS("%s", __func__);
 
 	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
 		CPRINTS("Can't reset: SOC is off");
 		return;
 	}
 
-	if (cold_reset) {
-		/*
-		 * Perform chipset_force_shutdown and mark forcing_coldreset.
-		 * Once in S5G3 state, check forcing_coldreset to power up.
-		 */
-		forcing_coldreset = 1;
-		chipset_force_shutdown();
-	} else {
-		/*
-		 * Send a pulse to SYS_RST to trigger a warm reset.
-		 */
-		gpio_set_level(GPIO_PCH_RCIN_L, 0);
-		usleep(32 * MSEC);
-		gpio_set_level(GPIO_PCH_RCIN_L, 1);
-	}
+	/*
+	 * Send a pulse to SYS_RST to trigger a warm reset.
+	 */
+	gpio_set_level(GPIO_PCH_RCIN_L, 0);
+	usleep(32 * MSEC);
+	gpio_set_level(GPIO_PCH_RCIN_L, 1);
 }
 
 void chipset_throttle_cpu(int throttle)