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| author | Keith Short <keithshort@chromium.org> | 2019-10-08 13:12:02 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-10-15 20:35:40 +0000 |
| commit | c6448a1a81aa86ef6d77a2667886a746d396d1b9 (patch) | |
| tree | 0a4c509a82689014642e49bd8f6f29579033449a /power | |
| parent | df8a8aa2b6674df68cc6710c53ddeeb7da05bd53 (diff) | |
| download | chrome-ec-c6448a1a81aa86ef6d77a2667886a746d396d1b9.tar.gz | |
cometlake: Cleanup GPIO_PCH_SYS_PWROK
Change GPIO_EC_PCH_SYS_PWROK to GPIO_PCH_SYS_PWROK on cometlake to
conform with naming convention used on other Intel processors.
Leave gpio.inc files unchanged and add a mapping from
GPIO_EC_PCH_SYS_PWROK to GPIO_PCH_SYS_PWROK in the board files.
BUG=none
BRANCH=none
TEST=make buildall -j
TEST=boot kohaku
Change-Id: I722cb06dd90ee5d7e426664508f54a5cbe19de4a
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1848251
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/cometlake.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/power/cometlake.c b/power/cometlake.c index b69b075db9..62d5fbe6f7 100644 --- a/power/cometlake.c +++ b/power/cometlake.c @@ -166,17 +166,17 @@ enum power_state power_handle_state(enum power_state state) case POWER_S0: /* - * Check value of PG_EC_ALL_SYS_PWRGD to see if EC_PCH_SYS_PWROK + * Check value of PG_EC_ALL_SYS_PWRGD to see if PCH_SYS_PWROK * needs to be changed. If it's low->high transition, requires a * 2msec delay. */ all_sys_pwrgd_in = gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD); - all_sys_pwrgd_out = gpio_get_level(GPIO_EC_PCH_SYS_PWROK); + all_sys_pwrgd_out = gpio_get_level(GPIO_PCH_SYS_PWROK); if (all_sys_pwrgd_in != all_sys_pwrgd_out) { if (all_sys_pwrgd_in) msleep(2); - gpio_set_level(GPIO_EC_PCH_SYS_PWROK, all_sys_pwrgd_in); + gpio_set_level(GPIO_PCH_SYS_PWROK, all_sys_pwrgd_in); } break; |