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author | Jes B. Klinke <jbk@chromium.org> | 2023-02-13 10:36:37 -0800 |
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committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2023-02-14 18:30:00 +0000 |
commit | b34c7aa7821d7b3e51587a8d35d3fc82fc3104ca (patch) | |
tree | 0c14639528bbdb2fd7065bfada6f70a12b462e64 /test/usb_prl.mocklist | |
parent | 5b671a552726c1dbded0cbec0b33ab2da89d3e85 (diff) | |
download | chrome-ec-b34c7aa7821d7b3e51587a8d35d3fc82fc3104ca.tar.gz |
board/hyperdebug: Atomic setting of gpio mode and level
Currently, we use `opentitantool transport init` to configure all pins
according to some "standard" initial values. This involves configuring
open drain / push pull as well as setting default levels.
Unfortunately, if a pin is for instance listed as being "open drain,
high level" as default (no active drive), we currently have to make the
choice of whether to first configure the pin as open drain output, or
first configure the output to high. If we first configure the level to
become 1, we run the risk that the pin was set as push pull, and it will
be actively be driven high for a fraction of a second, before it is set
to open drain, and goes floating. If we instead first configure the
mode to become open drain, then we risk that the pin was previously in
input mode, with a "leftover" value of 0 in the output register, meaning
that switching to open drain mode will briefly drive the pin drongly
down, before the level is set to 1.
In order to avoid glitches, this CL introduces a "gpio multiset"
command, which can be used to simultaneously set the output level, pin
mode, and weak pull configuration of the pin.
BUG=b:192262089
TEST=Watch tast test work
Change-Id: Ie16771e5cb676af02a0dabe454e4173721629b30
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4245899
Tested-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
Diffstat (limited to 'test/usb_prl.mocklist')
0 files changed, 0 insertions, 0 deletions