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| author | Yen Lin <yelin@nvidia.com> | 2014-12-08 12:22:09 -0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-12-17 21:08:20 +0000 |
| commit | ec12acc81f47e9b88517cd4a955414f7a1ee1cf6 (patch) | |
| tree | 89f0ae233acc097c53c92e8fbbb7799f9d33d9c3 /test | |
| parent | a7bae3588cb976405b90677a324de06c71fa3f48 (diff) | |
| download | chrome-ec-ec12acc81f47e9b88517cd4a955414f7a1ee1cf6.tar.gz | |
clock-stm32l: properly setting HSI/MSI clock based on the RM
According the STM32L RM, when writing to RCC_CFGR to change HSI or MSI
clock source, SWS bits of RCC_CFGR register have to be checked if the
new clock source is taken into account. Also, when writing ACC64 bit and
LATENCY bit to FLASH_ACR register, those bits have to be checked too.
Also changed in this CL is to disable MSI if HSI is enabled, and disable
HSI if MSI is enabled.
BUG=chrome-os-partner:32936
BRANCH=none
TEST=passed suspend_stress_test on big, blaze and nyan
Change-Id: I3ec660d149ecdec3ca3097239612bf2c542d0548
Signed-off-by: Yen Lin <yelin@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/234490
Reviewed-by: Kary Jin <karyj@nvidia.com>
Tested-by: Kary Jin <karyj@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit 400d9dca8c41f74cf0c2587e881707b80bb17d3d)
Reviewed-on: https://chromium-review.googlesource.com/236050
Diffstat (limited to 'test')
0 files changed, 0 insertions, 0 deletions