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| author | Nicolas Boichat <drinkcat@chromium.org> | 2018-07-05 16:54:46 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-09-21 00:50:59 -0700 |
| commit | 15dd79c1a2ab3355a7d7a0197fcacff973a001a2 (patch) | |
| tree | 29da6e71d014137ea52c9ff728b1ba1061119700 /third_party/boringssl/core/cortex-m/ghash.S | |
| parent | 4a237232c27c18d5367403d743d523509570e5cd (diff) | |
| download | chrome-ec-15dd79c1a2ab3355a7d7a0197fcacff973a001a2.tar.gz | |
aes-gcm: Adapt AES-GCM to build for EC
Update header, C code, trim unnecessary bits.
Also add a test with vectors taken from BoringSSL tests.
BRANCH=none
BUG=b:111160949
TEST=make run-aes -j
TEST=make BOARD=nocturne_fp test-aes -j
flash_fp_mcu aes.bin
runtest => pass
(C implementation speed: 909555 us for 1000 iterations)
(ASM implementation speed: 596690 us for 1000 iterations)
Change-Id: Ief54a8441d26ba44de4c3ac81e203cab7472269f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1141446
Commit-Ready: Nicolas Norvez <norvez@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
Diffstat (limited to 'third_party/boringssl/core/cortex-m/ghash.S')
| -rw-r--r-- | third_party/boringssl/core/cortex-m/ghash.S | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/third_party/boringssl/core/cortex-m/ghash.S b/third_party/boringssl/core/cortex-m/ghash.S index fafcb5c23b..a1eb97b9c5 100644 --- a/third_party/boringssl/core/cortex-m/ghash.S +++ b/third_party/boringssl/core/cortex-m/ghash.S @@ -8,12 +8,7 @@ @ in the file LICENSE in the source distribution or at @ https://www.openssl.org/source/license.html -#include <openssl/arm_arch.h> - -@ Silence ARMv8 deprecated IT instruction warnings. This file is used by both -@ ARMv7 and ARMv8 processors and does not use ARMv8 instructions. (ARMv8 PMULL -@ instructions are in aesv8-armx.pl.) -.arch armv7-a +#define __ARM_ARCH__ 7 .text #if defined(__thumb2__) || defined(__clang__) @@ -111,7 +106,7 @@ gcm_ghash_4bit: #ifdef __thumb2__ it pl #endif - ldrplb r12,[r2,r3] + ldrbpl r12,[r2,r3] eor r6,r6,r7,lsl#28 eor r7,r11,r7,lsr#4 @@ -124,7 +119,7 @@ gcm_ghash_4bit: #ifdef __thumb2__ it pl #endif - ldrplb r8,[r0,r3] + ldrbpl r8,[r0,r3] eor r4,r4,r5,lsl#28 eor r5,r9,r5,lsr#4 ldrh r9,[sp,r14] @@ -180,7 +175,7 @@ gcm_ghash_4bit: #ifdef __thumb2__ it ne #endif - ldrneb r12,[r2,#15] + ldrbne r12,[r2,#15] #if __ARM_ARCH__>=7 && defined(__ARMEL__) rev r6,r6 str r6,[r0,#4] @@ -270,7 +265,7 @@ gcm_gmult_4bit: #ifdef __thumb2__ it pl #endif - ldrplb r12,[r0,r3] + ldrbpl r12,[r0,r3] eor r6,r6,r7,lsl#28 eor r7,r11,r7,lsr#4 @@ -363,7 +358,7 @@ gcm_gmult_4bit: .word 0xe12fff1e @ interoperable with Thumb ISA:-) #endif .size gcm_gmult_4bit,.-gcm_gmult_4bit -#if __ARM_MAX_ARCH__>=7 +#ifdef __ARM_NEON__ .arch armv7-a .fpu neon |