Merge remote-tracking branch cros/main into firmware-fpmcu-dartmonkey-releasefirmware-fpmcu-dartmonkey-release

Generated by: ./util/update_release_branch.py --board dartmonkey --relevant_paths_file
./util/fingerprint-relevant-paths.txt firmware-fpmcu-dartmonkey-release

Relevant changes:

git log --oneline 6c1587ca70..28712dae9d -- board/nocturne_fp
board/dartmonkey common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
a0751778f4 board/nocturne_fp/ro_workarounds.c: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
58f0246dbe board/nocturne_fp/board_ro.c: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
84e53a65da board/nocturne_fp/board.h: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header

BRANCH=None
BUG=b:244387210 b:242720240 b:215613183 b:242720910 b:236386294
BUG=b:234181908 b:244781166 b:234781655 b:234143158 b:234181908
BUG=b:237344361 b:236025198 b:234181908 b:180945056 chromium:1098010
BUG=b:246424843 b:234181908 b:131913998
TEST=`make -j buildall`
TEST=./util/run_device_tests.py --board dartmonkey
     Test "aes": PASSED
     Test "cec": PASSED
     Test "cortexm_fpu": PASSED
     Test "crc": PASSED
     Test "flash_physical": PASSED
     Test "flash_write_protect": PASSED
     Test "fpsensor_hw": PASSED
     Test "fpsensor_spi_ro": PASSED
     Test "fpsensor_spi_rw": PASSED
     Test "fpsensor_uart_ro": PASSED
     Test "fpsensor_uart_rw": PASSED
     Test "mpu_ro": PASSED
     Test "mpu_rw": PASSED
     Test "mutex": PASSED
     Test "pingpong": PASSED
     Test "printf": PASSED
     Test "queue": PASSED
     Test "rollback_region0": PASSED
     Test "rollback_region1": PASSED
     Test "rollback_entropy": PASSED
     Test "rtc": PASSED
     Test "sha256": PASSED
     Test "sha256_unrolled": PASSED
     Test "static_if": PASSED
     Test "stdlib": PASSED
     Test "system_is_locked_wp_on": PASSED
     Test "system_is_locked_wp_off": PASSED
     Test "timer_dos": PASSED
     Test "utils": PASSED
     Test "utils_str": PASSED
     Test "panic_data_dartmonkey_v2.0.2887": PASSED
     Test "panic_data_nocturne_fp_v2.2.64": PASSED
     Test "panic_data_nami_fp_v2.2.144": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>

Change-Id: I2c312583a709fedae8fe11d92c22328c3b634bc7

1 files changed, 163 insertions, 182 deletions

diff --git a/util/ecst.h b/util/ecst.h
index 628eaebe9b..7d3dbbe153 100644
--- a/util/ecst.h
+++ b/util/ecst.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,149 +16,146 @@
 #include <stdio.h>
 #include <curses.h>
 
-
 /*---------------------------------------------------------------------------
   Defines
   --------------------------------------------------------------------------*/
 
 /* For the beauty */
-#define TRUE                            1
-#define FALSE                           0
+#define TRUE 1
+#define FALSE 0
 
 /* CHANGEME when the version is updated */
-#define T_VER                           1
-#define T_REV_MAJOR                     0
-#define T_REV_MINOR                     3
+#define T_VER 1
+#define T_REV_MAJOR 0
+#define T_REV_MINOR 3
 
 /* Header starts by default at 0x20000 */
-#define FIRMWARE_OFFSET_FROM_HEADER     0x40
+#define FIRMWARE_OFFSET_FROM_HEADER 0x40
 
-#define ARM_FW_ENTRY_POINT_OFFSET       0x04
+#define ARM_FW_ENTRY_POINT_OFFSET 0x04
 
 /* Some useful offsets inside the header */
-#define	HDR_ANCHOR_OFFSET                    0
-#define	HDR_EXTENDED_ANCHOR_OFFSET           4
-#define	HDR_SPI_MAX_CLK_OFFSET               6
-#define	HDR_SPI_READ_MODE_OFFSET             7
-#define	HDR_ERR_DETECTION_CONF_OFFSET        8
-#define	HDR_FW_LOAD_START_ADDR_OFFSET        9
-#define	HDR_FW_ENTRY_POINT_OFFSET            13
-#define	HDR_FW_ERR_DETECT_START_ADDR_OFFSET  17
-#define	HDR_FW_ERR_DETECT_END_ADDR_OFFSET    21
-#define	HDR_FW_LENGTH_OFFSET                 25
-#define	HDR_FLASH_SIZE_OFFSET                29
-#define HDR_RESERVED                         30
-#define	HDR_FW_HEADER_SIG_OFFSET             56
-#define HDR_FW_IMAGE_SIG_OFFSET              60
-
-
-#define FIRMW_CKSM_OFFSET               0x3C
+#define HDR_ANCHOR_OFFSET 0
+#define HDR_EXTENDED_ANCHOR_OFFSET 4
+#define HDR_SPI_MAX_CLK_OFFSET 6
+#define HDR_SPI_READ_MODE_OFFSET 7
+#define HDR_ERR_DETECTION_CONF_OFFSET 8
+#define HDR_FW_LOAD_START_ADDR_OFFSET 9
+#define HDR_FW_ENTRY_POINT_OFFSET 13
+#define HDR_FW_ERR_DETECT_START_ADDR_OFFSET 17
+#define HDR_FW_ERR_DETECT_END_ADDR_OFFSET 21
+#define HDR_FW_LENGTH_OFFSET 25
+#define HDR_FLASH_SIZE_OFFSET 29
+#define HDR_RESERVED 30
+#define HDR_FW_HEADER_SIG_OFFSET 56
+#define HDR_FW_IMAGE_SIG_OFFSET 60
+
+#define FIRMW_CKSM_OFFSET 0x3C
 
 /* Header field known values */
-#define FW_HDR_ANCHOR                   0x2A3B4D5E
-#define FW_HDR_EXT_ANCHOR_ENABLE        0xAB1E
-#define FW_HDR_EXT_ANCHOR_DISABLE       0x54E1
-#define FW_CRC_DISABLE                  0x00
-#define FW_CRC_ENABLE                   0x02
-#define HEADER_CRC_FIELDS_SIZE          8
+#define FW_HDR_ANCHOR 0x2A3B4D5E
+#define FW_HDR_EXT_ANCHOR_ENABLE 0xAB1E
+#define FW_HDR_EXT_ANCHOR_DISABLE 0x54E1
+#define FW_CRC_DISABLE 0x00
+#define FW_CRC_ENABLE 0x02
+#define HEADER_CRC_FIELDS_SIZE 8
 
-#define HDR_PTR_SIGNATURE               0x55AA650E
+#define HDR_PTR_SIGNATURE 0x55AA650E
 
-#define CKSMCRC_INV_BIT_OFFSET          0x1
+#define CKSMCRC_INV_BIT_OFFSET 0x1
 
 /* Some common Sizes */
-#define STR_SIZE                        200
-#define	ARG_SIZE                        100
-#define NAME_SIZE                       160
-#define BUFF_SIZE                       0x400
-#define HEADER_SIZE                     64
-#define TMP_STR_SIZE                    21
-#define PAD_VALUE                       0x00
-
+#define STR_SIZE 200
+#define ARG_SIZE 100
+#define NAME_SIZE 160
+#define BUFF_SIZE 0x400
+#define HEADER_SIZE 64
+#define TMP_STR_SIZE 21
+#define PAD_VALUE 0x00
 
-#define MAX_ARGS                        100
+#define MAX_ARGS 100
 
 /* Text Colors */
-#define TDBG                            0x02  /* Dark Green     */
-#define TPAS                            0x0A  /* light green    */
-#define TINF                            0x0B  /* light turquise */
-#define TERR                            0x0C  /* light red      */
-#define TUSG                            0x0E  /* light yellow   */
+#define TDBG 0x02 /* Dark Green     */
+#define TPAS 0x0A /* light green    */
+#define TINF 0x0B /* light turquise */
+#define TERR 0x0C /* light red      */
+#define TUSG 0x0E /* light yellow   */
 
 /* Indicates bin Command line parameters */
-#define BIN_FW_HDR_CRC_DISABLE          0x0001
-#define BIN_FW_CRC_DISABLE              0x0002
-#define BIN_FW_START                    0x0004
-#define BIN_FW_SIZE                     0x0008
-#define BIN_CK_FIRMWARE                 0x0010
-#define BIN_FW_CKS_START                0x0020
-#define BIN_FW_CKS_SIZE                 0x0040
-#define BIN_FW_CHANGE_SIG               0x0080
-#define BIN_FW_SPI_MAX_CLK              0x0100
-#define BIN_FW_LOAD_START_ADDR          0x0200
-#define BIN_FW_ENTRY_POINT              0x0400
-#define BIN_FW_LENGTH                   0x0800
-#define BIN_FW_HDR_OFFSET               0x1000
-#define	BIN_FW_USER_ARM_RESET           0x2000
-#define BIN_UNLIM_BURST_ENABLE          0x4000
-
-#define ECRP_OFFSET                     0x01
-#define ECRP_INPUT_FILE                 0x02
-#define ECRP_OUTPUT_FILE                0x04
-
-#define SPI_MAX_CLOCK_20_MHZ_VAL        20
-#define SPI_MAX_CLOCK_25_MHZ_VAL        25
-#define SPI_MAX_CLOCK_33_MHZ_VAL        33
-#define SPI_MAX_CLOCK_40_MHZ_VAL        40
-#define SPI_MAX_CLOCK_50_MHZ_VAL        50
-
-#define SPI_MAX_CLOCK_20_MHZ            0x00
-#define SPI_MAX_CLOCK_25_MHZ            0x01
-#define SPI_MAX_CLOCK_33_MHZ            0x02
-#define SPI_MAX_CLOCK_40_MHZ            0x03
-#define SPI_MAX_CLOCK_50_MHZ            0x04
-#define SPI_MAX_CLOCK_MASK              0xF8
-
-#define SPI_CLOCK_RATIO_1_VAL           1
-#define SPI_CLOCK_RATIO_2_VAL           2
-
-#define SPI_CLOCK_RATIO_1               0x07
-#define SPI_CLOCK_RATIO_2               0x08
-
-#define SPI_NORMAL_MODE_VAL             "normal"
-#define SPI_SINGLE_MODE_VAL             "fast"
-#define SPI_DUAL_MODE_VAL               "dual"
-#define SPI_QUAD_MODE_VAL               "quad"
-
-#define SPI_NORMAL_MODE                 0x00
-#define SPI_SINGLE_MODE                 0x01
-#define SPI_DUAL_MODE                   0x03
-#define SPI_QUAD_MODE                   0x04
-
-#define SPI_UNLIMITED_BURST_ENABLE      0x08
-
-#define FLASH_SIZE_1_MBYTES_VAL         1
-#define FLASH_SIZE_2_MBYTES_VAL         2
-#define FLASH_SIZE_4_MBYTES_VAL         4
-#define FLASH_SIZE_8_MBYTES_VAL         8
-#define FLASH_SIZE_16_MBYTES_VAL        16
-
-#define FLASH_SIZE_1_MBYTES             0x01
-#define FLASH_SIZE_2_MBYTES             0x03
-#define FLASH_SIZE_4_MBYTES             0x07
-#define FLASH_SIZE_8_MBYTES             0x0F
-#define FLASH_SIZE_16_MBYTES            0x1F
+#define BIN_FW_HDR_CRC_DISABLE 0x0001
+#define BIN_FW_CRC_DISABLE 0x0002
+#define BIN_FW_START 0x0004
+#define BIN_FW_SIZE 0x0008
+#define BIN_CK_FIRMWARE 0x0010
+#define BIN_FW_CKS_START 0x0020
+#define BIN_FW_CKS_SIZE 0x0040
+#define BIN_FW_CHANGE_SIG 0x0080
+#define BIN_FW_SPI_MAX_CLK 0x0100
+#define BIN_FW_LOAD_START_ADDR 0x0200
+#define BIN_FW_ENTRY_POINT 0x0400
+#define BIN_FW_LENGTH 0x0800
+#define BIN_FW_HDR_OFFSET 0x1000
+#define BIN_FW_USER_ARM_RESET 0x2000
+#define BIN_UNLIM_BURST_ENABLE 0x4000
+
+#define ECRP_OFFSET 0x01
+#define ECRP_INPUT_FILE 0x02
+#define ECRP_OUTPUT_FILE 0x04
+
+#define SPI_MAX_CLOCK_20_MHZ_VAL 20
+#define SPI_MAX_CLOCK_25_MHZ_VAL 25
+#define SPI_MAX_CLOCK_33_MHZ_VAL 33
+#define SPI_MAX_CLOCK_40_MHZ_VAL 40
+#define SPI_MAX_CLOCK_50_MHZ_VAL 50
+
+#define SPI_MAX_CLOCK_20_MHZ 0x00
+#define SPI_MAX_CLOCK_25_MHZ 0x01
+#define SPI_MAX_CLOCK_33_MHZ 0x02
+#define SPI_MAX_CLOCK_40_MHZ 0x03
+#define SPI_MAX_CLOCK_50_MHZ 0x04
+#define SPI_MAX_CLOCK_MASK 0xF8
+
+#define SPI_CLOCK_RATIO_1_VAL 1
+#define SPI_CLOCK_RATIO_2_VAL 2
+
+#define SPI_CLOCK_RATIO_1 0x07
+#define SPI_CLOCK_RATIO_2 0x08
+
+#define SPI_NORMAL_MODE_VAL "normal"
+#define SPI_SINGLE_MODE_VAL "fast"
+#define SPI_DUAL_MODE_VAL "dual"
+#define SPI_QUAD_MODE_VAL "quad"
+
+#define SPI_NORMAL_MODE 0x00
+#define SPI_SINGLE_MODE 0x01
+#define SPI_DUAL_MODE 0x03
+#define SPI_QUAD_MODE 0x04
+
+#define SPI_UNLIMITED_BURST_ENABLE 0x08
+
+#define FLASH_SIZE_1_MBYTES_VAL 1
+#define FLASH_SIZE_2_MBYTES_VAL 2
+#define FLASH_SIZE_4_MBYTES_VAL 4
+#define FLASH_SIZE_8_MBYTES_VAL 8
+#define FLASH_SIZE_16_MBYTES_VAL 16
+
+#define FLASH_SIZE_1_MBYTES 0x01
+#define FLASH_SIZE_2_MBYTES 0x03
+#define FLASH_SIZE_4_MBYTES 0x07
+#define FLASH_SIZE_8_MBYTES 0x0F
+#define FLASH_SIZE_16_MBYTES 0x1F
 
 /* Header fields default values. */
-#define SPI_MAX_CLOCK_DEFAULT           SPI_MAX_CLOCK_20_MHZ_VAL
-#define SPI_READ_MODE_DEFAULT           SPI_NORMAL_MODE
-#define FLASH_SIZE_DEFAULT              FLASH_SIZE_16_MBYTES_VAL
-#define	FW_CRC_START_ADDR               0x00000000
+#define SPI_MAX_CLOCK_DEFAULT SPI_MAX_CLOCK_20_MHZ_VAL
+#define SPI_READ_MODE_DEFAULT SPI_NORMAL_MODE
+#define FLASH_SIZE_DEFAULT FLASH_SIZE_16_MBYTES_VAL
+#define FW_CRC_START_ADDR 0x00000000
 
-#define ADDR_16_BYTES_ALIGNED_MASK      0x0000000F
-#define ADDR_4_BYTES_ALIGNED_MASK       0x00000003
+#define ADDR_16_BYTES_ALIGNED_MASK 0x0000000F
+#define ADDR_4_BYTES_ALIGNED_MASK 0x00000003
 
-#define MAX_FLASH_SIZE                  0x03ffffff
+#define MAX_FLASH_SIZE 0x03ffffff
 
 /* Chips: convert from name to index. */
 enum npcx_chip_ram_variant {
@@ -172,25 +169,25 @@ enum npcx_chip_ram_variant {
 	NPCX_CHIP_RAM_VAR_NONE
 };
 
-#define DEFAULT_CHIP                    NPCX5M5G
+#define DEFAULT_CHIP NPCX5M5G
 
 /* NPCX5 */
-#define NPCX5M5G_RAM_ADDR               0x100A8000
-#define NPCX5M5G_RAM_SIZE               0x20000
-#define NPCX5M6G_RAM_ADDR               0x10088000
-#define NPCX5M6G_RAM_SIZE               0x40000
+#define NPCX5M5G_RAM_ADDR 0x100A8000
+#define NPCX5M5G_RAM_SIZE 0x20000
+#define NPCX5M6G_RAM_ADDR 0x10088000
+#define NPCX5M6G_RAM_SIZE 0x40000
 /* NPCX7 */
-#define NPCX7M5X_RAM_ADDR               0x100A8000
-#define NPCX7M5X_RAM_SIZE               0x20000
-#define NPCX7M6X_RAM_ADDR               0x10090000
-#define NPCX7M6X_RAM_SIZE               0x40000
-#define NPCX7M7X_RAM_ADDR               0x10070000
-#define NPCX7M7X_RAM_SIZE               0x60000
+#define NPCX7M5X_RAM_ADDR 0x100A8000
+#define NPCX7M5X_RAM_SIZE 0x20000
+#define NPCX7M6X_RAM_ADDR 0x10090000
+#define NPCX7M6X_RAM_SIZE 0x40000
+#define NPCX7M7X_RAM_ADDR 0x10070000
+#define NPCX7M7X_RAM_SIZE 0x60000
 /* NPCX9 */
-#define NPCX9M3X_RAM_ADDR               0x10080000
-#define NPCX9M3X_RAM_SIZE               0x50000
-#define NPCX9M6X_RAM_ADDR               0x10090000
-#define NPCX9M6X_RAM_SIZE               0x40000
+#define NPCX9M3X_RAM_ADDR 0x10080000
+#define NPCX9M3X_RAM_SIZE 0x50000
+#define NPCX9M6X_RAM_ADDR 0x10090000
+#define NPCX9M6X_RAM_SIZE 0x40000
 
 /*---------------------------------------------------------------------------
   Typedefs
@@ -198,47 +195,39 @@ enum npcx_chip_ram_variant {
 
 /* Parameters for Binary manipulation */
 struct tbinparams {
-	unsigned int	anchor;
-	unsigned short	ext_anchor;
-	unsigned char	spi_max_clk;
-	unsigned char	spi_clk_ratio;
-	unsigned char	spi_read_mode;
-	unsigned char	err_detec_cnf;
-	unsigned int	fw_load_addr;
-	unsigned int	fw_ep;
-	unsigned int	fw_err_detec_s_addr;
-	unsigned int	fw_err_detec_e_addr;
-	unsigned int	fw_len;
-	unsigned int	flash_size;
-	unsigned int	hdr_crc;
-	unsigned int	fw_crc;
-	unsigned int	fw_hdr_offset;
-	unsigned int	bin_params;
+	unsigned int anchor;
+	unsigned short ext_anchor;
+	unsigned char spi_max_clk;
+	unsigned char spi_clk_ratio;
+	unsigned char spi_read_mode;
+	unsigned char err_detec_cnf;
+	unsigned int fw_load_addr;
+	unsigned int fw_ep;
+	unsigned int fw_err_detec_s_addr;
+	unsigned int fw_err_detec_e_addr;
+	unsigned int fw_len;
+	unsigned int flash_size;
+	unsigned int hdr_crc;
+	unsigned int fw_crc;
+	unsigned int fw_hdr_offset;
+	unsigned int bin_params;
 } bin_params_struct;
 
-enum verbose_level {
-	NO_VERBOSE = 0,
-	REGULAR_VERBOSE,
-	SUPER_VERBOSE
-};
+enum verbose_level { NO_VERBOSE = 0, REGULAR_VERBOSE, SUPER_VERBOSE };
 
-enum calc_type {
-	CALC_TYPE_NONE	= 0,
-	CALC_TYPE_CHECKSUM ,
-	CALC_TYPE_CRC
-};
+enum calc_type { CALC_TYPE_NONE = 0, CALC_TYPE_CHECKSUM, CALC_TYPE_CRC };
 
 struct chip_info {
-	unsigned int	ram_addr;
-	unsigned int   ram_size;
+	unsigned int ram_addr;
+	unsigned int ram_size;
 } chip_info_struct;
 
 /*------------------------------------------------------------------------*/
 /* CRC Variable bit operation macros                                      */
 /*------------------------------------------------------------------------*/
-#define NUM_OF_BYTES					32
-#define READ_VAR_BIT(var, nb)			(((var) >> (nb)) & 0x1)
-#define SET_VAR_BIT(var, nb, val)		((var) |= ((val)<<(nb)))
+#define NUM_OF_BYTES 32
+#define READ_VAR_BIT(var, nb) (((var) >> (nb)) & 0x1)
+#define SET_VAR_BIT(var, nb, val) ((var) |= ((val) << (nb)))
 
 /*---------------------------------------------------------------------------
   Functions Declaration
@@ -254,35 +243,27 @@ void init_calculation(unsigned int *check_sum_crc);
 void finalize_calculation(unsigned int *check_sum_crc);
 void update_calculation_information(unsigned char crc_con_dat);
 
-
 /* Checksum calculation etc. (BIN Specific) */
 int calc_header_crc_bin(unsigned int *pointer_header_checksum);
-int calc_firmware_csum_bin(unsigned int *p_cksum,
-						   unsigned int fw_offset,
-						   unsigned int fw_length);
+int calc_firmware_csum_bin(unsigned int *p_cksum, unsigned int fw_offset,
+			   unsigned int fw_length);
 
 /* Checksum calculation etc. (ERP Specific) */
 int calc_erp_csum_bin(unsigned short *region_pointer_header_checksum,
-					  unsigned int region_pointer_ofs);
+		      unsigned int region_pointer_ofs);
 
 /* No words - General */
 void exit_with_usage(void);
-int copy_file_to_file(char *dst_file_name,
-					  char *src_file_name,
-					  int offset,
-					  int origin);
-int write_to_file(unsigned int write_value,
-				  unsigned int offset,
-				  unsigned char num_of_bytes,
-				  char *print_string);
-int read_from_file(unsigned int offset,
-				   unsigned char size_to_read,
-				   unsigned int *read_value,
-				   char *print_string);
+int copy_file_to_file(char *dst_file_name, char *src_file_name, int offset,
+		      int origin);
+int write_to_file(unsigned int write_value, unsigned int offset,
+		  unsigned char num_of_bytes, char *print_string);
+int read_from_file(unsigned int offset, unsigned char size_to_read,
+		   unsigned int *read_value, char *print_string);
 
 /* Nice Particular Printf - General */
-__attribute__((__format__(__printf__, 2, 3)))
-void my_printf(int error_level, char *fmt, ...);
+__attribute__((__format__(__printf__, 2, 3))) void my_printf(int error_level,
+							     char *fmt, ...);
 
 int str_cmp_no_case(const char *s1, const char *s2);
 int get_file_length(FILE *stream);