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| author | Wealian Liao <whliao@nuvoton.corp-partner.google.com> | 2020-09-04 13:25:30 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-09-09 14:53:05 +0000 |
| commit | 176915de592d6316fb3e63f51e5535a9d89fcb18 (patch) | |
| tree | 50a1256d8d8d5c4d6d8c32bbda788d3fdba7c69e /util/ecst.h | |
| parent | d500d5fc51a9939d19dd141d3ba32565d518183a (diff) | |
| download | chrome-ec-176915de592d6316fb3e63f51e5535a9d89fcb18.tar.gz | |
util: ecst: add support for chip variant npcx9
Allow ecst tool to compose the correct firmware header for npcx993f &
npcx996f.
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST=with the related CLs, change CHIP_VARIANT to npcx996f in
board/npcx9_evb/build.mk; "BOARD=npcx9_evb make";
check the image can be built and the image header is correct.
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: Ia48b19854850a642a2f4ed97ca45230f46fbd65c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2393403
Reviewed-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'util/ecst.h')
| -rw-r--r-- | util/ecst.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/util/ecst.h b/util/ecst.h index f99caf4ed8..04d696c7c5 100644 --- a/util/ecst.h +++ b/util/ecst.h @@ -167,21 +167,30 @@ enum npcx_chip_ram_variant { NPCX7M5 = 2, NPCX7M6 = 3, NPCX7M7 = 4, + NPCX9M3 = 5, + NPCX9M6 = 6, NPCX_CHIP_RAM_VAR_NONE }; #define DEFAULT_CHIP NPCX5M5G +/* NPCX5 */ #define NPCX5M5G_RAM_ADDR 0x100A8000 #define NPCX5M5G_RAM_SIZE 0x20000 #define NPCX5M6G_RAM_ADDR 0x10088000 #define NPCX5M6G_RAM_SIZE 0x40000 +/* NPCX7 */ #define NPCX7M5X_RAM_ADDR 0x100A8000 #define NPCX7M5X_RAM_SIZE 0x20000 #define NPCX7M6X_RAM_ADDR 0x10090000 #define NPCX7M6X_RAM_SIZE 0x40000 #define NPCX7M7X_RAM_ADDR 0x10070000 #define NPCX7M7X_RAM_SIZE 0x60000 +/* NPCX9 */ +#define NPCX9M3X_RAM_ADDR 0x10080000 +#define NPCX9M3X_RAM_SIZE 0x50000 +#define NPCX9M6X_RAM_ADDR 0x10090000 +#define NPCX9M6X_RAM_SIZE 0x40000 /*--------------------------------------------------------------------------- Typedefs |