util: improve uartupdatetool (UUT) mechanism

The original UUT mechanism has the limitation that the image size cannot
exceed the code RAM size. Hence, it only allows to flash the EC firmware
by programming RO and RW images seperately.

In this CL, we introduce the "--auto" flag in uartupdattool.
It will divide the firmware into segments (4K bytes) and program
the segments one by one.
It also simplifies the function flash_npcx_uut() in flash_ec because
some actions are moved into the uartupdatetool with auto flag enabled.

BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=
------------------------------------------------------------------------
1. Connect the servo connector (J24) on npcx7 EVB to servo board v2 via
flex cable.
2. Manually turn the switch SW1.6 to "ON" on npcx7 EVB.
3. Reset ec by issuing Power-Up or VCC1_RST reset.
4. Manually turn the switch SW1.6 to "OFF" on npcx7 EVB.
5. Move npcx7_evb from array BOARDS_NPCX_7M7X_JTAG to BOARDS_NPCX_UUT in
flash_ec.
6. "./util/flash_ec --board=npcx7_evb" or
   "./util/flash_ec --board=npcx7_evb --ro"
(Note: this line in flash_ec must be removed in step 6:
https://chromium.googlesource.com/chromiumos/platform/ec/+/master/util/flash_ec#961)

Change-Id: Ifdb6a40ef88c6a9fb435169e158fd615100237cf
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1043825
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>

1 files changed, 9 insertions, 48 deletions

diff --git a/util/flash_ec b/util/flash_ec
index 593a4ede1e..2260b53674 100755
--- a/util/flash_ec
+++ b/util/flash_ec
@@ -447,7 +447,11 @@ fi
 
 LOCAL_BUILD=
 if [[ -n "${EC_DIR}" ]]; then
-	LOCAL_BUILD="${EC_DIR}/build/${BOARD}/${EC_FILE}"
+	if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] ; then
+		LOCAL_BUILD="${EC_DIR}/build/${BOARD}/RO/${EC_FILE}"
+	else
+		LOCAL_BUILD="${EC_DIR}/build/${BOARD}/${EC_FILE}"
+	fi
 fi
 
 # Get baseboard from build system if present
@@ -953,18 +957,9 @@ function flash_npcx_uut() {
 
 	BUILD_PATH="${EC_DIR}/build/${BOARD}"
 	MONITOR_PATH="${BUILD_PATH}/chip/npcx/spiflashfw"
-	IMG_RO="${BUILD_PATH}/RO/ec.RO.flat"
-	IMG_RW="${BUILD_PATH}/RW/ec.RW.bin"
 	MON="${MONITOR_PATH}/npcx_monitor.bin"
-	MON_HDR_RO="${MONITOR_PATH}/monitor_hdr_ro.bin"
-	MON_HDR_RW="${MONITOR_PATH}/monitor_hdr_rw.bin"
-	# The start address to restore monitor header binary
-	MON_HDR_ADDR="0x200C3000"
 	# The start address to restore monitor firmware binary
 	MON_ADDR="0x200C3020"
-	# Read the address where the EC image should be loaded from monitor header.
-	# Default: It is equilvalant to the beginning of code RAM address.
-	EC_IMG_ADDR="0x"$(xxd -e ${MON_HDR_RO} | cut -d' ' -f4)
 
 	if [ ! -x "$NPCX_UUT" ]; then
 		die "no NPCX UART Update Tool found."
@@ -987,45 +982,11 @@ function flash_npcx_uut() {
 
 	# Remove the prefix "/dev/" because uartupdatetool will add it.
 	EC_UART=${EC_UART#/dev/}
-	MON_PARAMS="--port ${EC_UART} --baudrate 115200"
-
-	# Read the RO image size
-	EC_IMG_SIZE=$(printf "%08X" $(stat -c "%s" ${IMG_RO}))
-	# Covert RO image size to little endian
-	EC_IMG_SIZE_LE=${EC_IMG_SIZE:6:2}${EC_IMG_SIZE:4:2}${EC_IMG_SIZE:2:2}${EC_IMG_SIZE:0:2}
-	# Replace the filed of image size in monitor header with the actual RO image size.
-	T=/tmp/mon_hdr_ro.$$
-	xxd -g4 ${MON_HDR_RO} | awk -v s="$EC_IMG_SIZE_LE" 'NR==1 {$3=s}1' | xxd -r > ${T}
-
-	info "Start to flash RO image.."
-	# Start to program EC RO image
-	# Load monitor header binary to address 0x200C3000
-	${NPCX_UUT} ${MON_PARAMS} --opr wr --addr ${MON_HDR_ADDR} --file ${T}
-	# Load monitor binary to address 0x200C3020
-	${NPCX_UUT} ${MON_PARAMS} --opr wr --addr ${MON_ADDR} --file ${MON}
-	# Load RO image to Code RAM range.
-	${NPCX_UUT} ${MON_PARAMS} --opr wr --addr ${EC_IMG_ADDR} --file ${IMG_RO}
-	# Execute the monitor to program RO image on SPI flash
-	${NPCX_UUT} ${MON_PARAMS} --opr call --addr ${MON_ADDR}
-
-	# Read the RW image size
-	EC_IMG_SIZE=$(printf "%08X" $(stat -c "%s" ${IMG_RW}))
-	# Covert RW image size to little endian
-	EC_IMG_SIZE_LE=${EC_IMG_SIZE:6:2}${EC_IMG_SIZE:4:2}${EC_IMG_SIZE:2:2}${EC_IMG_SIZE:0:2}
-	# Replace the filed of image size in monitor header with the actual RW image size.
-	T=/tmp/mon_hdr_rw.$$
-	xxd -g4 ${MON_HDR_RW} | awk -v s="$EC_IMG_SIZE_LE" 'NR==1 {$3=s}1' | xxd -r > ${T}
-
-	info "Start to flash RW image.."
-	# Start to program EC RW image
-	# Load monitor header binary to address 0x200C3000
-	${NPCX_UUT} ${MON_PARAMS} --opr wr --addr ${MON_HDR_ADDR} --file ${T}
+	UUT_PARAMS="--port ${EC_UART} --baudrate 115200"
+
 	# Load monitor binary to address 0x200C3020
-	${NPCX_UUT} ${MON_PARAMS} --opr wr --addr ${MON_ADDR} --file ${MON}
-	# Load RW image to Code RAM range.
-	${NPCX_UUT} ${MON_PARAMS} --opr wr --addr ${EC_IMG_ADDR} --file ${IMG_RW}
-	# Execute the monitor to program RW image on SPI flash
-	${NPCX_UUT} ${MON_PARAMS} --opr call --addr ${MON_ADDR}
+	${NPCX_UUT} ${UUT_PARAMS} --opr wr --addr ${MON_ADDR} --file ${MON}
+	${NPCX_UUT} ${UUT_PARAMS} --auto --offset ${FLAGS_offset} --file ${IMG}
 
 	# Reconnect the EC-3PO interpreter to the UART.
 	dut_control ${MCU}_ec3po_interp_connect:on || \