diff options
author | CHLin <CHLIN56@nuvoton.com> | 2017-12-14 13:49:33 +0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-01-02 21:32:18 -0800 |
commit | 749632d30fcbb56fa6cb319b10d6379ff3559de4 (patch) | |
tree | 7fbc2792fbe7937600a57f3dbd79a9e271658438 /util/flash_ec | |
parent | f4700dac616a3ac42acf34b149ab741f9f5bcdbc (diff) | |
download | chrome-ec-749632d30fcbb56fa6cb319b10d6379ff3559de4.tar.gz |
util/flash_ec: npcx7 supports programming SPI flash via UART
This CL adds scripts to support updating ec image to the SPI flash by
UUT(UART Update Tool) for npcx ec. A new array BOARDS_NPCX_UUT is
introduced to include the board name which will use the UUT mechanism.
The detail of test setup/procedure is listed below:
1. Connect the following singals between npcx7 evb and Servo board v2.
NPCX7 EVB Servo V2
---------------------------------------
GPIO64/CR_SIN <--> UART1_SERVO_DUT_TX
GPIO65/CR_SOUT <--> UART1_DUT_SERVO_TX
VDD_3.3V <--> PPDUT_UART1_VREF
2. Manually pull the UUT mode strap pin(GPIO65/CR_SOUT) to ground with a
10 KOhm resistor.
3. Assert a EC VCC1_RST reset or issue a Power-Up reset.
4. Remove the pull-down in step 2.
5. Move npcx7_evb from array BOARDS_NPCX_7M6X_JTAG to BOARDS_NPCX_UUT in
flash_ec.
6. ./util/flash_ec --board=npcx7_evb.
BRANCH=none
BUG=none
TEST=Follow the steps above. Dump the SPI flash content to a file via
JTAG. Compare the file and ec image. Make sure their content is all
the same. Check the ec can reboot after programming.
Run "sysjump rw"; make sure RW image works well.
Change-Id: Iada5acb53179bdb78459c4fea7488fd2691575b6
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/826763
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'util/flash_ec')
-rwxr-xr-x | util/flash_ec | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/util/flash_ec b/util/flash_ec index 0edeee8365..ec5a6fa893 100755 --- a/util/flash_ec +++ b/util/flash_ec @@ -129,6 +129,9 @@ BOARDS_NPCX_INT_SPI=( zoombini ) +BOARDS_NPCX_UUT=( +) + BOARDS_NRF51=( hadoken ) @@ -240,6 +243,8 @@ elif $(in_array "${BOARDS_NPCX_SPI[@]}" "${BOARD}"); then CHIP="npcx_spi" elif $(in_array "${BOARDS_NPCX_INT_SPI[@]}" "${BOARD}"); then CHIP="npcx_spi" +elif $(in_array "${BOARDS_NPCX_UUT[@]}" "${BOARD}"); then + CHIP="npcx_uut" elif $(in_array "${BOARDS_NRF51[@]}" "${BOARD}"); then CHIP="nrf51" elif $(in_array "${BOARDS_MEC1322[@]}" "${BOARD}"); then @@ -816,6 +821,82 @@ function flash_npcx_jtag() { flash_openocd } +function flash_npcx_uut() { + TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH" + NPCX_UUT=$(PATH="${TOOL_PATH}" which Uartupdatetool) + EC_UART="$(servo_ec_uart)" + + BUILD_PATH="${EC_DIR}/build/${BOARD}" + MONITOR_PATH="${BUILD_PATH}/chip/npcx/spiflashfw" + IMG_RO="${BUILD_PATH}/RO/ec.RO.flat" + IMG_RW="${BUILD_PATH}/RW/ec.RW.bin" + MON="${MONITOR_PATH}/npcx_monitor.bin" + MON_HDR_RO="${MONITOR_PATH}/monitor_hdr_ro.bin" + MON_HDR_RW="${MONITOR_PATH}/monitor_hdr_rw.bin" + # The start address to restore monitor header binary + MON_HDR_ADDR="0x200C3000" + # The start address to restore monitor firmware binary + MON_ADDR="0x200C3020" + # Read the address where the EC image should be loaded from monitor header. + # Default: It is equilvalant to the beginning of code RAM address. + EC_IMG_ADDR="0x"$(xxd -e ${MON_HDR_RO} | cut -d' ' -f4) + + if [ ! -x "$NPCX_UUT" ]; then + die "no NPCX UART Update Tool found." + fi + + info "Using: NPCX UART Update Tool" + info "${MCU} UART pty : ${EC_UART}" + claim_pty ${EC_UART} + + # Remove the prefix "/dev/" because Uartupdatetool will add it. + EC_UART=${EC_UART#/dev/} + MON_PARAMS="-port ${EC_UART} -baudrate 115200" + + # Read the RO image size + EC_IMG_SIZE=$(printf "%08X" $(stat -c "%s" ${IMG_RO})) + # Covert RO image size to little endian + EC_IMG_SIZE_LE=${EC_IMG_SIZE:6:2}${EC_IMG_SIZE:4:2}${EC_IMG_SIZE:2:2}${EC_IMG_SIZE:0:2} + # Replace the filed of image size in monitor header with the actual RO image size. + T=/tmp/mon_hdr_ro.$$ + xxd -g4 ${MON_HDR_RO} | awk -v s="$EC_IMG_SIZE_LE" 'NR==1 {$3=s}1' | xxd -r > ${T} + + info "Start to flash RO image.." + # Start to program EC RO image + # Load monitor header binary to address 0x200C3000 + ${NPCX_UUT} ${MON_PARAMS} -opr wr -addr ${MON_HDR_ADDR} -file ${T} + # Load monitor binary to address 0x200C3020 + ${NPCX_UUT} ${MON_PARAMS} -opr wr -addr ${MON_ADDR} -file ${MON} + # Load RO image to Code RAM range. + ${NPCX_UUT} ${MON_PARAMS} -opr wr -addr ${EC_IMG_ADDR} -file ${IMG_RO} + # Execute the monitor to program RO image on SPI flash + ${NPCX_UUT} ${MON_PARAMS} -opr call -addr ${MON_ADDR} + + # Read the RW image size + EC_IMG_SIZE=$(printf "%08X" $(stat -c "%s" ${IMG_RW})) + # Covert RW image size to little endian + EC_IMG_SIZE_LE=${EC_IMG_SIZE:6:2}${EC_IMG_SIZE:4:2}${EC_IMG_SIZE:2:2}${EC_IMG_SIZE:0:2} + # Replace the filed of image size in monitor header with the actual RW image size. + T=/tmp/mon_hdr_rw.$$ + xxd -g4 ${MON_HDR_RW} | awk -v s="$EC_IMG_SIZE_LE" 'NR==1 {$3=s}1' | xxd -r > ${T} + + info "Start to flash RW image.." + # Start to program EC RW image + # Load monitor header binary to address 0x200C3000 + ${NPCX_UUT} ${MON_PARAMS} -opr wr -addr ${MON_HDR_ADDR} -file ${T} + # Load monitor binary to address 0x200C3020 + ${NPCX_UUT} ${MON_PARAMS} -opr wr -addr ${MON_ADDR} -file ${MON} + # Load RW image to Code RAM range. + ${NPCX_UUT} ${MON_PARAMS} -opr wr -addr ${EC_IMG_ADDR} -file ${IMG_RW} + # Execute the monitor to program RW image on SPI flash + ${NPCX_UUT} ${MON_PARAMS} -opr call -addr ${MON_ADDR} + + # Reconnect the EC-3PO interpreter to the UART. + dut_control ${MCU}_ec3po_interp_connect:on || \ + warn "hdctools cannot reconnect the EC-3PO interpreter to" \ + "the UART." +} + function flash_npcx_5m5g_jtag() { flash_npcx_jtag } |