diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2015-08-06 18:16:22 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-08-12 18:12:27 +0000 |
| commit | 9fdcfe00ca8fd62bced35b970768df2c90b967df (patch) | |
| tree | 866b45f4208799c9ca833594be62cc31764528c7 /util/flash_ec | |
| parent | 5b4fd77df38e03b2618b817131101aaeddee03b5 (diff) | |
| download | chrome-ec-9fdcfe00ca8fd62bced35b970768df2c90b967df.tar.gz | |
nuc:Using LRESET interrupt to re-initialize LPC settings after warm boot
Fixed bug during polling port 0x204 by BIOS.
We should set processing flag before reading command byte in ISR to prevent
EC_LPC_STATUS_FROM_HOST and EC_LPC_STATUS_PROCESSING bits are both low.
Modified drivers:
1. gpio.c: Add LRESET ISR.
2. lpc.c: Fixed bug during polling port 0x204 by BIOS.
3. flash_ec: Reset ec before flashing ec
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I8e557f2e2be41a7a9d40c03c775313b12668f283
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/291210
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'util/flash_ec')
| -rwxr-xr-x | util/flash_ec | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/util/flash_ec b/util/flash_ec index 0eaca8c85e..96bdb85fbc 100755 --- a/util/flash_ec +++ b/util/flash_ec @@ -429,6 +429,9 @@ function flash_npcx() { OCD_CMDS="init; flash_npcx_all ${IMG_PATH} ${FLAGS_offset}; shutdown;" fi + # Reset the EC + ec_reset + flash_openocd } |