diff options
| author | Myles Watson <mylesgw@chromium.org> | 2015-05-28 12:12:13 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-09 01:17:52 +0000 |
| commit | b793546316544eb6cb48362ad91d60c42dbee9e4 (patch) | |
| tree | 57eb355248b13a1165333261d3603efe1c4b9c44 /util/openocd/npcx.cfg | |
| parent | 4271b631a374549881c44203758fa2179d8b8179 (diff) | |
| download | chrome-ec-b793546316544eb6cb48362ad91d60c42dbee9e4.tar.gz | |
flash_ec: move openocd configs from chip/ to util/
Avoid duplicating servo configurations for every chip.
BRANCH=none
BUG=chrome-os-partner:22990
TEST=None. This is an intermediate step to make it clear what's happening.
CQ-DEPEND=CL:273950
Change-Id: I448543b6ab9d39423955e8d2589b6035c59e838a
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273906
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'util/openocd/npcx.cfg')
| -rw-r--r-- | util/openocd/npcx.cfg | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/util/openocd/npcx.cfg b/util/openocd/npcx.cfg new file mode 100644 index 0000000000..cd00715d72 --- /dev/null +++ b/util/openocd/npcx.cfg @@ -0,0 +1,63 @@ +# Copyright (c) 2014 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# nuvoton-m4 devices support both JTAG and SWD transports. +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME npcx5m5g +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 16kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +#jtag scan chain +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4BA00477 +} + +#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position \ + $_CHIPNAME.cpu -work-area-phys 0x200C0000 \ + -work-area-size $_WORKAREASIZE + +# JTAG speed +adapter_khz 100 + +adapter_nsrst_delay 100 +if {$using_jtag} { + jtag_ntrst_delay 100 +} + +# use srst to perform a system reset +cortex_m reset_config srst + +#reset configuration +reset_config trst_and_srst + +$_TARGETNAME configure -event reset-start { + echo "NPCX5M5G Reset..." + adapter_khz 1000 + halt +} |