diff options
| author | CHLin <CHLIN56@nuvoton.com> | 2017-12-14 18:17:57 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-01-03 22:42:59 -0800 |
| commit | e358a5521d3dda93d9ca219352a4f27c20d49a18 (patch) | |
| tree | 7edfbc9e276e4055ee2961e595b9a4922e888dcb /util/openocd/npcx_cmds.tcl | |
| parent | 5b1c4868d762f5f0c27748c690fdfbad54d03b9c (diff) | |
| download | chrome-ec-e358a5521d3dda93d9ca219352a4f27c20d49a18.tar.gz | |
util/openocd: modify the openocd srcipts for npcx UUT
In the CL:826909, the name and the restore address of ec_spiflash lfw
are modified becaue of introducing the UUT. This CL modified the openocd
scripts to follow the changes of the lfw.
BRANCH=none
BUG=none
TEST=Apply CL:826906 and "BOARD=npcx7_evb make";
Run cmd "./util/flash_ec --board=npcx7_evb" to flash ec image;
Make sure the ec firmware can be updated with the new npcx_minotor lfw
+ this CL via JTAG on Servo v2.
Change-Id: If622f83e2d2132d66b390bcee30c77e7a9d5f7bd
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/828341
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'util/openocd/npcx_cmds.tcl')
| -rw-r--r-- | util/openocd/npcx_cmds.tcl | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/util/openocd/npcx_cmds.tcl b/util/openocd/npcx_cmds.tcl index ca44343084..5edc88e5f2 100644 --- a/util/openocd/npcx_cmds.tcl +++ b/util/openocd/npcx_cmds.tcl @@ -9,6 +9,7 @@ source [find mem_helper.tcl] proc flash_npcx {image_path cram_addr image_offset image_size spifw_image} { set UPLOAD_FLAG 0x200C4000; + set UUT_TAG 0x200C3000; echo "*** NPCX Reset and halt CPU first ***" reset halt @@ -19,7 +20,7 @@ proc flash_npcx {image_path cram_addr image_offset image_size spifw_image} { load_image $image_path $cram_addr # Upload program spi image FW to lower 16KB Data RAM - load_image $spifw_image 0x200C0000 + load_image $spifw_image 0x200C3020 # Set sp to upper 16KB Data RAM reg sp 0x200C8000 @@ -28,10 +29,13 @@ proc flash_npcx {image_path cram_addr image_offset image_size spifw_image} { # Set spi program size of uploaded image reg r1 $image_size # Set pc to start of spi program function - reg pc 0x200C0001 + reg pc 0x200C3021 # Clear upload flag mww $UPLOAD_FLAG 0x0 + # Clear UUT Tag + mww $UUT_TAG 0x0 + echo "*** Program ... ***" # Start to program spi flash resume @@ -88,7 +92,7 @@ proc flash_npcx_ro {chip_name image_dir image_offset} { # images path set ro_image_path $image_dir/RO/ec.RO.flat - set spifw_image $image_dir/chip/npcx/spiflashfw/ec_npcxflash.bin + set spifw_image $image_dir/chip/npcx/spiflashfw/npcx_monitor.bin # Halt CPU first halt @@ -118,7 +122,7 @@ proc flash_npcx_all {chip_name image_dir image_offset} { # images path set ro_image_path $image_dir/RO/ec.RO.flat set rw_image_path $image_dir/RW/ec.RW.bin - set spifw_image $image_dir/chip/npcx/spiflashfw/ec_npcxflash.bin + set spifw_image $image_dir/chip/npcx/spiflashfw/npcx_monitor.bin # Halt CPU first halt |