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| author | Ian Chao <mlchao@nuvoton.com> | 2015-07-09 14:53:00 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-25 01:22:32 +0000 |
| commit | 14bd917343489c09033f0f9c97e7951d5cb2aeec (patch) | |
| tree | 1722f9d92f5ffb2525eebec68f86b1aab06b3e71 /util/openocd | |
| parent | 7de0037538bd0016c9202ad289655cbf4f4d90aa (diff) | |
| download | chrome-ec-14bd917343489c09033f0f9c97e7951d5cb2aeec.tar.gz | |
nuc:
Add ECST tool to modify the header used by npcx booter.
Modified drivers:
1. i2c.c: Modify for i2c_port design.
2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue.
3. hwtimer.c: Fixed bug whcih event expired time is behide current timer.
4. lpc.c: Add intializing host settings after pltrst is deasserted.
5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle
when gpio is any-edge trigger mode.
6. task.c: Add workaround method for hard fault issue.
7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE
8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO
9. lpc.c: fixed obe interrupt bug during 8042 initialization
10.Adjust path of flat files for new Makefile rules
11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/284036
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'util/openocd')
| -rw-r--r-- | util/openocd/npcx.cfg | 6 | ||||
| -rw-r--r-- | util/openocd/npcx_cmds.tcl | 18 |
2 files changed, 11 insertions, 13 deletions
diff --git a/util/openocd/npcx.cfg b/util/openocd/npcx.cfg index d42580a907..73b1957f3c 100644 --- a/util/openocd/npcx.cfg +++ b/util/openocd/npcx.cfg @@ -46,9 +46,7 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position \ adapter_khz 100 adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} +jtag_ntrst_delay 100 # use srst to perform a system reset cortex_m reset_config srst @@ -58,6 +56,6 @@ reset_config trst_and_srst $_TARGETNAME configure -event reset-start { echo "NPCX5M5G Reset..." - adapter_khz 1000 halt + adapter_khz 1000 } diff --git a/util/openocd/npcx_cmds.tcl b/util/openocd/npcx_cmds.tcl index a32afccf03..51db7f635a 100644 --- a/util/openocd/npcx_cmds.tcl +++ b/util/openocd/npcx_cmds.tcl @@ -10,6 +10,9 @@ source [find mem_helper.tcl] proc flash_npcx {image_path image_offset image_size spifw_image} { set UPLOAD_FLAG 0x200C4000; + echo "*** NPCX Reset and halt CPU first ***" + reset halt + # Clear whole 96KB Code RAM mwb 0x100A8000 0xFF 0x18000 # Upload binary image to Code RAM @@ -34,7 +37,7 @@ proc flash_npcx {image_path image_offset image_size spifw_image} { resume # Wait for any pending flash operations to complete - while {[expr [mrw $UPLOAD_FLAG] & 0x01] == 0} { sleep 1 } + while {[expr [mrw $UPLOAD_FLAG] & 0x01] == 0} { sleep 1000 } if {[expr [mrw $UPLOAD_FLAG] & 0x02] == 0} { echo "*** Program Fail ***" @@ -58,7 +61,6 @@ proc flash_npcx_ro {image_dir image_offset} { # Halt CPU first halt - adapter_khz 1000 # diable MPU for Data RAM mww $MPU_RNR 0x1 @@ -81,8 +83,8 @@ proc flash_npcx_all {image_dir image_offset} { set flash_size 0x800000 # images path - set ro_image_path $image_dir/ec.RO.flat - set rw_image_path $image_dir/ec.RW.bin + set ro_image_path $image_dir/RO/ec.RO.flat + set rw_image_path $image_dir/RW/ec.RW.bin set spifw_image $image_dir/chip/npcx/spiflashfw/ec_npcxflash.bin # images offset @@ -91,8 +93,6 @@ proc flash_npcx_all {image_dir image_offset} { # Halt CPU first halt - adapter_khz 1000 - # diable MPU for Data RAM mww $MPU_RNR 0x1 mww $MPU_RASR 0x0 @@ -109,7 +109,7 @@ proc flash_npcx_all {image_dir image_offset} { } -proc halt_npcx_cpu { } { - echo "*** Halt CPU first ***" - halt +proc reset_halt_cpu { } { + echo "*** NPCX Reset and halt CPU first ***" + reset halt } |