npcx7_evb: Add initial board driver of npcx7 ec evb.

Add the evaluation board driver of npcx7 series ec for testing. If you
received the evb which ec is 128-pins package, please notice it has
the following limitations.

a. No GPIOD7/E0 pins.
b. No I2C4_0, I2C4_1, I2C5_1 and I2C6_1 ports.
c. No ADC7, ADC8 and ADC9 channels.
d. No JTAG port 1.
e. Do not enable CONFIG_HIBERNATE_PSL since no PSL circuit on evb.

This CL also includes:
1. Modified reset config from srst to sysresetreq in openocd/npcx.cfg.
   Make sure openocd driver can reset ec by using NVIC_SYSRESETREQ.
2. Add flash utilities for npcx7 ec in openocd/npcx_cmds.tcl.
3. Add npcx7_evb support in flash_ec.

BRANCH=none
BUG=none
TEST=Passed all npcx7 drivers verification on the evb no matter which
     ec's package is 128 or 144 pins package.

Change-Id: I8224d97cd66ce483d70816f47b2e124308f1b69c
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/505832
Reviewed-by: Randall Spangler <rspangler@chromium.org>

2 files changed, 24 insertions, 3 deletions

diff --git a/util/openocd/npcx.cfg b/util/openocd/npcx.cfg
index 42b04dcd3d..b32f62b363 100644
--- a/util/openocd/npcx.cfg
+++ b/util/openocd/npcx.cfg
@@ -48,8 +48,8 @@ adapter_khz 100
 adapter_nsrst_delay 100
 jtag_ntrst_delay 100
 
-# use srst to perform a system reset
-cortex_m reset_config srst
+# use sysresetreq to perform a system reset
+cortex_m reset_config sysresetreq
 
 #reset configuration
 reset_config trst_and_srst
diff --git a/util/openocd/npcx_cmds.tcl b/util/openocd/npcx_cmds.tcl
index 579aa3834e..ca44343084 100644
--- a/util/openocd/npcx_cmds.tcl
+++ b/util/openocd/npcx_cmds.tcl
@@ -71,6 +71,17 @@ proc flash_npcx5m6g {image_path image_offset spifw_image} {
 	echo "*** Finish program npcx5m6g ***\r\n"
 }
 
+proc flash_npcx7m6x {image_path image_offset spifw_image} {
+	# 192 KB for RO & RW regions
+	set fw_size   0x30000
+	# Code RAM start address
+	set cram_addr 0x10090000
+
+	echo "*** Start to program npcx7m6f/g/k with $image_path ***"
+	flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image
+	echo "*** Finish program npcx7m6f/g/k ***\r\n"
+}
+
 proc flash_npcx_ro {chip_name image_dir image_offset} {
 	set MPU_RNR  0xE000ED98;
 	set MPU_RASR 0xE000EDA0;
@@ -92,6 +103,9 @@ proc flash_npcx_ro {chip_name image_dir image_offset} {
 	} elseif {$chip_name == "npcx_5m6g_jtag"} {
 		# program RO region
 		flash_npcx5m6g $ro_image_path $image_offset $spifw_image
+	} elseif {$chip_name == "npcx_7m6x_jtag"} {
+		# program RO region
+		flash_npcx7m6x $ro_image_path $image_offset $spifw_image
 	} else {
 		echo $chip_name "no supported."
 	}
@@ -121,12 +135,19 @@ proc flash_npcx_all {chip_name image_dir image_offset} {
 		# program RW region
 		flash_npcx5m5g $rw_image_path $rw_image_offset $spifw_image
 	} elseif {$chip_name == "npcx_5m6g_jtag"} {
-		# RW images offset - 512 KB
+		# RW images offset - 256 KB
 		set rw_image_offset  [expr ($image_offset + 0x40000)]
 		# program RO region
 		flash_npcx5m6g $ro_image_path $image_offset $spifw_image
 		# program RW region
 		flash_npcx5m6g $rw_image_path $rw_image_offset $spifw_image
+	} elseif {$chip_name == "npcx_7m6x_jtag"} {
+		# RW images offset - 256 KB
+		set rw_image_offset  [expr ($image_offset + 0x40000)]
+		# program RO region
+		flash_npcx7m6x $ro_image_path $image_offset $spifw_image
+		# program RW region
+		flash_npcx7m6x $rw_image_path $rw_image_offset $spifw_image
 	} else {
 		echo $chip_name "no supported."
 	}