Revert "cr50: debounce successive TPM reset pulses"

This reverts commit 4805196e894a73a2a1285f1cd622d160ad248f77.

Reason for revert: We aren't planning on landing this in the branch.
Reduce the difference between TOT and the branch by reverting this.

BUG=b:164130916
TEST=run ccd open with TOT image

Original change's description:
> cr50: debounce successive TPM reset pulses
>
> Some platforms generate more than one pulse when resetting, many Intel
> SOCs generate two pulses, some other chips could go even higher.
>
> TPM reset on Cr50 is processed asynchronously, repetitive pulses
> result in multiple reset processing cycles.In case pulses are coming
> too soon one after another this could cause some race conditions.
>
> Let's ignore repetitive reset pulses unless there has been an attempt
> by the host to read a register (which is usually the very first action
> of the AP when booting up).
>
> BRANCH=cr50, cr50-mp
> BUG=none
> TEST=observed that only one reset is happening on an Octopus device,
>      while there are two pulses present on the PLT_RST_L line.
>
>      Verified proper reboot multiple times in a row.
>
> Change-Id: Ie1b124d41be0388bd8e12d0084827782de62cfa0
> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1755059
> Reviewed-by: Mary Ruthven <mruthven@chromium.org>

Bug: none
Change-Id: Ifbe8afea87c522c94cf9ab73cca8a1489ec3956b
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2485927

0 files changed, 0 insertions, 0 deletions