flash_ec: move openocd configs from chip/ to util/

Avoid duplicating servo configurations for every chip.

BRANCH=none
BUG=chrome-os-partner:22990
TEST=None.  This is an intermediate step to make it clear what's happening.
CQ-DEPEND=CL:273950

Change-Id: I448543b6ab9d39423955e8d2589b6035c59e838a
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273906
Reviewed-by: Randall Spangler <rspangler@chromium.org>

5 files changed, 262 insertions, 0 deletions

diff --git a/util/openocd/lm4x_cmds.tcl b/util/openocd/lm4x_cmds.tcl
new file mode 100644
index 0000000000..601d03e445
--- /dev/null
+++ b/util/openocd/lm4x_cmds.tcl
@@ -0,0 +1,67 @@
+# Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Command automation for Blizzard LM4F chip
+
+# Program internal flash
+
+proc flash_lm4 {path offset} {
+	#set firstsect [expr {$offset / 1024}];
+	#set lastsect [expr {($offset + $size) / 1024 - 1}];
+	reset halt;
+	flash write_image erase $path $offset;
+	reset
+}
+
+proc flash_auron { } {
+	flash_lm4 ../../../build/auron/ec.bin 0
+}
+
+proc flash_bds { } {
+	flash_lm4 ../../../build/bds/ec.bin 0
+}
+
+proc flash_rambi { } {
+	flash_lm4 ../../../build/rambi/ec.bin 0
+}
+
+proc flash_samus { } {
+	flash_lm4 ../../../build/samus/ec.bin 0
+}
+
+proc flash_samus_ro { } {
+	flash_lm4 ../../../build/samus/ec.RO.flat 0
+}
+
+proc flash_samus_rw { } {
+	flash_lm4 ../../../build/samus/ec.RW.bin 131072
+}
+
+proc flash_rambi_ro { } {
+	flash_lm4 ../../../build/rambi/ec.RO.flat 0
+}
+
+proc flash_rambi_rw { } {
+	flash_lm4 ../../../build/rambi/ec.RW.bin 131072
+}
+
+# Auron have pstate following RO
+proc unprotect_auron { } {
+	reset halt
+	flash erase_sector 0 126 127
+	reset
+}
+
+# Boot a software using internal RAM only
+
+proc ramboot_lm4 {path} {
+	reset halt
+	load_image $path 0x20000000 bin
+	reg 15 0x20000400
+	resume
+}
+
+proc ramboot_bds { } {
+	ramboot_lm4 ../../../build/bds/ec.RO.flat
+}
diff --git a/util/openocd/npcx.cfg b/util/openocd/npcx.cfg
new file mode 100644
index 0000000000..cd00715d72
--- /dev/null
+++ b/util/openocd/npcx.cfg
@@ -0,0 +1,63 @@
+# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# nuvoton-m4 devices support both JTAG and SWD transports.
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME npcx5m5g
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set  _WORKAREASIZE $WORKAREASIZE
+} else {
+   set  _WORKAREASIZE 0x8000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4BA00477
+}
+
+#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position \
+		$_CHIPNAME.cpu -work-area-phys 0x200C0000 \
+		-work-area-size $_WORKAREASIZE
+
+# JTAG speed
+adapter_khz 100
+
+adapter_nsrst_delay 100
+if {$using_jtag} {
+ jtag_ntrst_delay 100
+}
+
+# use srst to perform a system reset
+cortex_m reset_config srst
+
+#reset configuration
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event reset-start {
+	echo "NPCX5M5G Reset..."
+	adapter_khz 1000
+	halt
+}
diff --git a/util/openocd/npcx_chip.cfg b/util/openocd/npcx_chip.cfg
new file mode 100644
index 0000000000..5294b733fd
--- /dev/null
+++ b/util/openocd/npcx_chip.cfg
@@ -0,0 +1,4 @@
+interface jlink
+
+source [find npcx.cfg]
+source [find npcx_cmds.tcl]
diff --git a/util/openocd/npcx_cmds.tcl b/util/openocd/npcx_cmds.tcl
new file mode 100644
index 0000000000..a32afccf03
--- /dev/null
+++ b/util/openocd/npcx_cmds.tcl
@@ -0,0 +1,115 @@
+# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Command automation for NPCX5M5G chip
+
+# Program spi flash
+source [find mem_helper.tcl]
+
+proc flash_npcx {image_path image_offset image_size spifw_image} {
+	set UPLOAD_FLAG 0x200C4000;
+
+	# Clear whole 96KB Code RAM
+	mwb 0x100A8000 0xFF 0x18000
+	# Upload binary image to Code RAM
+	load_image $image_path 0x100A8000
+
+	# Upload program spi image FW to lower 16KB Data RAM
+	load_image $spifw_image 0x200C0000
+
+	# Set sp to upper 16KB Data RAM
+	reg sp 0x200C8000
+	# Set spi offset address of uploaded image
+	reg r0 $image_offset
+	# Set spi program size of uploaded image
+	reg r1 $image_size
+	# Set pc to start of spi program function
+	reg pc 0x200C0001
+	# Clear upload flag
+	mww $UPLOAD_FLAG 0x0
+
+	echo "*** Program ...  ***"
+	# Start to program spi flash
+	resume
+
+	# Wait for any pending flash operations to complete
+	while {[expr [mrw $UPLOAD_FLAG] & 0x01] == 0} { sleep 1 }
+
+	if {[expr [mrw $UPLOAD_FLAG] & 0x02] == 0} {
+		echo "*** Program Fail ***"
+	} else {
+		echo "*** Program Done ***"
+	}
+
+	# Halt CPU
+	halt
+}
+
+proc flash_npcx_ro {image_dir image_offset} {
+	set MPU_RNR  0xE000ED98;
+	set MPU_RASR 0xE000EDA0;
+
+	# 96 KB for RO& RW regions
+	set fw_size  0x18000
+	# images path
+	set ro_image_path $image_dir/ec.RO.flat
+	set spifw_image	$image_dir/chip/npcx/spiflashfw/ec_npcxflash.bin
+
+	# Halt CPU first
+	halt
+	adapter_khz 1000
+
+	# diable MPU for Data RAM
+	mww $MPU_RNR  0x1
+	mww $MPU_RASR 0x0
+
+	echo "*** Start to program RO region ***"
+	# Write to lower 96kB from offset
+	flash_npcx $ro_image_path $image_offset $fw_size $spifw_image
+	echo "*** Finish program RO region ***"
+
+}
+
+proc flash_npcx_all {image_dir image_offset} {
+	set MPU_RNR  0xE000ED98;
+	set MPU_RASR 0xE000EDA0;
+
+	# 96 KB for RO& RW regions
+	set fw_size  0x18000
+	# 8M spi-flash
+	set flash_size 0x800000
+
+	# images path
+	set ro_image_path $image_dir/ec.RO.flat
+	set rw_image_path $image_dir/ec.RW.bin
+	set spifw_image	$image_dir/chip/npcx/spiflashfw/ec_npcxflash.bin
+
+	# images offset
+	set rw_image_offset  [expr ($image_offset + 0x20000)]
+
+	# Halt CPU first
+	halt
+
+	adapter_khz 1000
+
+	# diable MPU for Data RAM
+	mww $MPU_RNR  0x1
+	mww $MPU_RASR 0x0
+
+	echo "*** Start to program RO region ***"
+	# Write to lower 96kB from offset
+	flash_npcx $ro_image_path $image_offset $fw_size $spifw_image
+	echo "*** Finish program RO region ***\r\n"
+
+	echo "*** Start to program RW region ***"
+	# Write to upper 96kB from offset
+	flash_npcx $rw_image_path $rw_image_offset $fw_size $spifw_image
+	echo "*** Finish program RW region ***\r\n"
+
+}
+
+proc halt_npcx_cpu { } {
+	echo "*** Halt CPU first ***"
+	halt
+}
diff --git a/util/openocd/servo.cfg b/util/openocd/servo.cfg
new file mode 100644
index 0000000000..7d8fd77f7c
--- /dev/null
+++ b/util/openocd/servo.cfg
@@ -0,0 +1,13 @@
+telnet_port 4444
+gdb_port 3333
+gdb_memory_map enable
+gdb_flash_program enable
+
+interface ftdi
+ftdi_vid_pid 0x18d1 0x5002
+ftdi_layout_init 0x0c08 0x0f1b
+ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
+
+source [find target/stellaris.cfg]
+source [find lm4x_cmds.tcl]