diff options
author | Mulin Chao <mlchao@nuvoton.com> | 2016-03-09 14:27:53 +0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2016-03-15 21:49:36 -0700 |
commit | 3424deb4813365abbad0b02c5fb8c29dcc4ffc74 (patch) | |
tree | 24e6aeea8adf5e1ffd2e7b9db15807a17d7c1c1c /util | |
parent | 750b4525da7c1336968b0d881e18571670ae307c (diff) | |
download | chrome-ec-3424deb4813365abbad0b02c5fb8c29dcc4ffc74.tar.gz |
npcx: Add 256KB alignment of RO & RW regions for npcx5m6g.
Since npcx5m6g has larger than 128 KB code ram for FW, the original
alignment between RO & RW regions isn't suitable for new chip.
Therefore, we add 256KB alignment of them for npcx5m6g.
In order to program the flash used by npcx5m6g, we add new board array,
BOARDS_NPCX_5M6G_JTAG, in flash_ec to distinguish which flash layout
ec used. In npcx_cmds.tcl, add new script funcs such as flash_npcx5m5g
and flash_npcx5m6g to program flash with different layout.
Modified sources:
1. config_flash_layout.h: Add 256KB alignment of RO & RW regions for
npcx5m6g.
2. util/flash_ec: Add new board array, BOARDS_NPCX_5M6G_JTAG, to
distinguish which flash layout ec used.
3. openocd/npcx_cmds.tcl: Add new script funcs to program flash with
different layout.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I0ace31d96d6df2c423b66d508d30cefb0b82ed6c
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/331903
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'util')
-rwxr-xr-x | util/flash_ec | 23 | ||||
-rw-r--r-- | util/openocd/npcx.cfg | 2 | ||||
-rw-r--r-- | util/openocd/npcx_cmds.tcl | 87 |
3 files changed, 74 insertions, 38 deletions
diff --git a/util/flash_ec b/util/flash_ec index 6a1839d4a2..9aa737ddab 100755 --- a/util/flash_ec +++ b/util/flash_ec @@ -84,11 +84,14 @@ BOARDS_STM32_DFU=( twinkie ) -BOARDS_NPCX_JTAG=( +BOARDS_NPCX_5M5G_JTAG=( npcx_evb npcx_evb_arm ) +BOARDS_NPCX_5M6G_JTAG=( +) + BOARDS_NPCX_SPI=( wheatley ) @@ -158,8 +161,10 @@ elif $(in_array "${BOARDS_STM32[@]}" "${BOARD}"); then elif $(in_array "${BOARDS_STM32_DFU[@]}" "${BOARD}"); then CHIP="stm32_dfu" NEED_SERVO="no" -elif $(in_array "${BOARDS_NPCX_JTAG[@]}" "${BOARD}"); then - CHIP="npcx_jtag" +elif $(in_array "${BOARDS_NPCX_5M5G_JTAG[@]}" "${BOARD}"); then + CHIP="npcx_5m5g_jtag" +elif $(in_array "${BOARDS_NPCX_5M6G_JTAG[@]}" "${BOARD}"); then + CHIP="npcx_5m6g_jtag" elif $(in_array "${BOARDS_NPCX_SPI[@]}" "${BOARD}"); then CHIP="npcx_spi" elif $(in_array "${BOARDS_NRF51[@]}" "${BOARD}"); then @@ -539,10 +544,10 @@ function flash_npcx_jtag() { OCD_CHIP_CFG="npcx_chip.cfg" if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] ; then # Program RO region only - OCD_CMDS="init; flash_npcx_ro ${IMG_PATH} ${FLAGS_offset}; shutdown;" + OCD_CMDS="init; flash_npcx_ro ${CHIP} ${IMG_PATH} ${FLAGS_offset}; shutdown;" else # Program all EC regions - OCD_CMDS="init; flash_npcx_all ${IMG_PATH} ${FLAGS_offset}; shutdown;" + OCD_CMDS="init; flash_npcx_all ${CHIP} ${IMG_PATH} ${FLAGS_offset}; shutdown;" fi # Reset the EC @@ -551,6 +556,14 @@ function flash_npcx_jtag() { flash_openocd } +function flash_npcx_5m5g_jtag() { + flash_npcx_jtag +} + +function flash_npcx_5m6g_jtag() { + flash_npcx_jtag +} + function flash_npcx_spi() { flash_flashrom } diff --git a/util/openocd/npcx.cfg b/util/openocd/npcx.cfg index 73b1957f3c..42b04dcd3d 100644 --- a/util/openocd/npcx.cfg +++ b/util/openocd/npcx.cfg @@ -55,7 +55,7 @@ cortex_m reset_config srst reset_config trst_and_srst $_TARGETNAME configure -event reset-start { - echo "NPCX5M5G Reset..." + echo "NPCX Reset..." halt adapter_khz 1000 } diff --git a/util/openocd/npcx_cmds.tcl b/util/openocd/npcx_cmds.tcl index 51db7f635a..a21b804997 100644 --- a/util/openocd/npcx_cmds.tcl +++ b/util/openocd/npcx_cmds.tcl @@ -7,16 +7,16 @@ # Program spi flash source [find mem_helper.tcl] -proc flash_npcx {image_path image_offset image_size spifw_image} { +proc flash_npcx {image_path cram_addr image_offset image_size spifw_image} { set UPLOAD_FLAG 0x200C4000; echo "*** NPCX Reset and halt CPU first ***" reset halt - # Clear whole 96KB Code RAM - mwb 0x100A8000 0xFF 0x18000 + # Clear whole Code RAM + mwb $cram_addr 0xFF $image_size # Upload binary image to Code RAM - load_image $image_path 0x100A8000 + load_image $image_path $cram_addr # Upload program spi image FW to lower 16KB Data RAM load_image $spifw_image 0x200C0000 @@ -49,14 +49,34 @@ proc flash_npcx {image_path image_offset image_size spifw_image} { halt } -proc flash_npcx_ro {image_dir image_offset} { +proc flash_npcx5m5g {image_path image_offset spifw_image} { + # 96 KB for RO & RW regions + set fw_size 0x18000 + # Code RAM start address + set cram_addr 0x100A8000 + + echo "*** Start to program npcx5m5g with $image_path ***" + flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image + echo "*** Finish program npcx5m5g ***\r\n" +} + +proc flash_npcx5m6g {image_path image_offset spifw_image} { + # 224 KB for RO & RW regions + set fw_size 0x38000 + # Code RAM start address + set cram_addr 0x10088000 + + echo "*** Start to program npcx5m6g with $image_path ***" + flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image + echo "*** Finish program npcx5m6g ***\r\n" +} + +proc flash_npcx_ro {chip_name image_dir image_offset} { set MPU_RNR 0xE000ED98; set MPU_RASR 0xE000EDA0; - # 96 KB for RO& RW regions - set fw_size 0x18000 # images path - set ro_image_path $image_dir/ec.RO.flat + set ro_image_path $image_dir/RO/ec.RO.flat set spifw_image $image_dir/chip/npcx/spiflashfw/ec_npcxflash.bin # Halt CPU first @@ -66,30 +86,26 @@ proc flash_npcx_ro {image_dir image_offset} { mww $MPU_RNR 0x1 mww $MPU_RASR 0x0 - echo "*** Start to program RO region ***" - # Write to lower 96kB from offset - flash_npcx $ro_image_path $image_offset $fw_size $spifw_image - echo "*** Finish program RO region ***" - + if {$chip_name == "npcx_5m5g_jtag"} { + # program RO region + flash_npcx5m5g $ro_image_path $image_offset $spifw_image + } elseif {$chip_name == "npcx_5m6g_jtag"} { + # program RO region + flash_npcx5m6g $ro_image_path $image_offset $spifw_image + } else { + echo $chip_name "no supported." + } } -proc flash_npcx_all {image_dir image_offset} { +proc flash_npcx_all {chip_name image_dir image_offset} { set MPU_RNR 0xE000ED98; set MPU_RASR 0xE000EDA0; - # 96 KB for RO& RW regions - set fw_size 0x18000 - # 8M spi-flash - set flash_size 0x800000 - # images path set ro_image_path $image_dir/RO/ec.RO.flat set rw_image_path $image_dir/RW/ec.RW.bin set spifw_image $image_dir/chip/npcx/spiflashfw/ec_npcxflash.bin - # images offset - set rw_image_offset [expr ($image_offset + 0x20000)] - # Halt CPU first halt @@ -97,16 +113,23 @@ proc flash_npcx_all {image_dir image_offset} { mww $MPU_RNR 0x1 mww $MPU_RASR 0x0 - echo "*** Start to program RO region ***" - # Write to lower 96kB from offset - flash_npcx $ro_image_path $image_offset $fw_size $spifw_image - echo "*** Finish program RO region ***\r\n" - - echo "*** Start to program RW region ***" - # Write to upper 96kB from offset - flash_npcx $rw_image_path $rw_image_offset $fw_size $spifw_image - echo "*** Finish program RW region ***\r\n" - + if {$chip_name == "npcx_5m5g_jtag"} { + # RW images offset - 128 KB + set rw_image_offset [expr ($image_offset + 0x20000)] + # program RO region + flash_npcx5m5g $ro_image_path $image_offset $spifw_image + # program RW region + flash_npcx5m5g $rw_image_path $rw_image_offset $spifw_image + } elseif {$chip_name == "npcx_5m6g_jtag"} { + # RW images offset - 512 KB + set rw_image_offset [expr ($image_offset + 0x40000)] + # program RO region + flash_npcx5m6g $ro_image_path $image_offset $spifw_image + # program RW region + flash_npcx5m6g $rw_image_path $rw_image_offset $spifw_image + } else { + echo $chip_name "no supported." + } } proc reset_halt_cpu { } { |