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| author | Zhuohao Lee <zhuohao@chromium.org> | 2020-05-25 23:40:56 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-06-08 06:09:40 +0000 |
| commit | 766553c62683bd93bea403f25219e3ae5ab921e5 (patch) | |
| tree | 54636ac06cbc51bbba2b231b5fad6ef0fdd76a8c /util | |
| parent | 2bb86028ddaa556fcb5edbaf0d44697e4e3bae22 (diff) | |
| download | chrome-ec-766553c62683bd93bea403f25219e3ae5ab921e5.tar.gz | |
flash_fp_mcu: fix the volteer gpio setting
Due to the latest coreboot change, the gpiochip252 and gpiochip445
were removed and the gpiochip152 was added. Besides, the GPIO pin
also changed. This patch fixes the gpio pin setting.
BUG=b:156993750
BRANCH=none
TEST=ran flash_fp_mcu on the Volteer
Change-Id: I54082eea90e85746976d427523cfc0b53e87ddda
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2214876
Tested-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-by: Alex Levin <levinale@chromium.org>
Diffstat (limited to 'util')
| -rw-r--r-- | util/flash_fp_mcu | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/util/flash_fp_mcu b/util/flash_fp_mcu index bfa97f301a..d6d40179c6 100644 --- a/util/flash_fp_mcu +++ b/util/flash_fp_mcu @@ -293,24 +293,24 @@ config_nocturne() { } config_volteer() { - check_gpio_chip_exists "gpiochip252" - check_gpio_chip_exists "gpiochip445" + check_gpio_chip_exists "gpiochip152" readonly SPIDEV="/dev/spidev1.0" - # See - # third_party/coreboot/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h - # for pin name to number mapping. - # Examine `cat /sys/kernel/debug/pinctrl/INT34C5:02/gpio-ranges` and - # `cat /sys/kernel/debug/pinctrl/INT34C5:00/gpio-ranges` on a volteer - # device to determine gpio number from pin number. - - # FPMCU RST_ODL is on GPP_C23 = 252 + (211 - 188) = 275 - readonly GPIO_NRST=275 - # FPMCU BOOT0 is on GPP_C22 = 252 + (210 - 188) = 274 - readonly GPIO_BOOT0=274 - # FP_PWR_EN is on GPP_A21 = 445 + 63 = 508 - readonly GPIO_PWREN=508 + # See kernel/v5.4/drivers/pinctrl/intel/pinctrl-tigerlake.c + # for pin name and pin number. + # Examine `cat /sys/kernel/debug/pinctrl/INT34C5:00/gpio-ranges` on a + # volteer device to determine gpio number from pin number. + # For example: GPP_C23 is UART2_CTS which can be queried from EDS + # the pin number is 194. From the gpio-ranges, the gpio value is + # 408 + (194-171) = 431 + + # FPMCU RST_ODL is on GPP_C23 = 408 + (194 - 171) = 431 + readonly GPIO_NRST=431 + # FPMCU BOOT0 is on GPP_C22 = 408 + (193 - 171) = 430 + readonly GPIO_BOOT0=430 + # FP_PWR_EN is on GPP_A21 = 216 + (63 - 42) = 237 + readonly GPIO_PWREN=237 } # The "platform name" corresponds to the underlying board (reference design) |