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author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2021-08-06 12:55:25 -0700 |
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committer | Commit Bot <commit-bot@chromium.org> | 2022-03-15 18:05:13 +0000 |
commit | dcf99a4a0a2f818df91f22e47f46a3e8243b64ae (patch) | |
tree | 8f8a95e84abbccbddad03d98e2f9953246ca414c /zephyr/Kconfig.powerseq | |
parent | c3dd6d0fc27f0d844dced10e27210efe76b1e344 (diff) | |
download | chrome-ec-dcf99a4a0a2f818df91f22e47f46a3e8243b64ae.tar.gz |
power: Add base code for Meteorlake power sequencing
Added base code for Meteorlake power sequencing. Implementation closely
follows Intel Icelake power sequencing as reference and modified the
logic based on Meteorlake Platform Development Guide.
BUG=b:223985632
BRANCH=none
TEST=Able to boot MTLRVP to S0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Change-Id: Ia551a1e226c648d9f23aff05ad3d44c3735a2495
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3516600
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'zephyr/Kconfig.powerseq')
-rw-r--r-- | zephyr/Kconfig.powerseq | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/zephyr/Kconfig.powerseq b/zephyr/Kconfig.powerseq index 10459ed8ce..ab01f81b42 100644 --- a/zephyr/Kconfig.powerseq +++ b/zephyr/Kconfig.powerseq @@ -124,6 +124,7 @@ config PLATFORM_EC_POWERSEQ_S4 depends on PLATFORM_EC_ESPI_VW_SLP_S5 default y if AP_X86_INTEL_TGL default y if AP_X86_INTEL_ADL + default y if AP_X86_INTEL_MTL help Advertise S4 residency capabilities to the AP. This is required for AP hibernate (suspend-to-disk) on Intel platforms with Key Locker @@ -144,6 +145,14 @@ config CHIPSET_ALDERLAKE_SLG4BD44540 Use this for AlderLake power sequencing with the Silego chips. +config PLATFORM_EC_POWERSEQ_METEORLAKE + bool "Use common Meteorlake code for power sequencing" + depends on AP_X86_INTEL_MTL + default n + help + Use the Meteorlake common code for power sequencing. Note that + this applies to Meteorlake and potentially future SoCs. + menuconfig PLATFORM_EC_POWERSEQ_ICELAKE bool "Use common Icelake code for power sequencing" depends on AP_X86_INTEL_TGL |