diff options
| author | Wealian Liao <whliao@nuvoton.corp-partner.google.com> | 2021-07-16 11:02:20 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-07-27 15:57:21 +0000 |
| commit | c4e335d6851438aa2767189ef84dfefecca92869 (patch) | |
| tree | 8a3d4403f971875c2ccf9e1c9c09c85757730476 /zephyr/app/ec/chip | |
| parent | 15d5e2039030d22d2a65870542e7200f5f7fa335 (diff) | |
| download | chrome-ec-c4e335d6851438aa2767189ef84dfefecca92869.tar.gz | |
zephyr: npcx: Add default config for npcx7m6fb & npcx9m6f
NPCX series (NPCX7/9) uses the most same config in chromium projects.
This CL adds default config for npcx7m6fb & npcx9m6f. So we can use
the same config style.
Moreover, fix CROS_EC_RW_MEM_OFF for npcx9 series.
BUG=none
BRANCH=none
TEST=zmake testall
TEST=npcx9_evb get 'version' correct in RW image.
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I6cbd014d006aa68851231173477c8f22e234af6f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3033229
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Yuval Peress <peress@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'zephyr/app/ec/chip')
| -rw-r--r-- | zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 | 60 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 | 23 |
2 files changed, 25 insertions, 58 deletions
diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 index 26b36509ad..3c59d5405e 100644 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 +++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 @@ -8,54 +8,16 @@ if SOC_SERIES_NPCX7 -if SOC_NPCX7M6FC - # +# NPCX796FB: 1024 KiB Flash, 192 KiB code RAM, 62 KiB data RAM # NPCX796FC: 512 KiB Flash, 192 KiB code RAM, 62 KiB data RAM -# - -# Code RAM base for NPCX796FC -config CROS_EC_PROGRAM_MEMORY_BASE - default 0x10090000 - -config CROS_EC_RAM_BASE - default 0x200c0000 - -config CROS_EC_DATA_RAM_SIZE - default 0x00010000 - -config CROS_EC_RAM_SIZE - default 0x0000f800 - -config FLASH_SIZE - default 512 - -config CROS_EC_RO_MEM_OFF - default 0x0 - -# Image size limited by code RAM size (192 KiB) -config CROS_EC_RO_SIZE - default 0x30000 - -# RW firmware in program memory - Identical to RO, only one image loaded at a -# time. -config CROS_EC_RW_MEM_OFF - default 0x0 - -config CROS_EC_RW_SIZE - default 0x30000 - -endif # SOC_NPCX7M6FC - -if SOC_NPCX7M7FC - -# # NPCX797FC: 512 KiB Flash, 320 KiB code RAM, 62 KiB data RAM # -# Code RAM base for NPCX797FC +# Code RAM base for NPCX7 series config CROS_EC_PROGRAM_MEMORY_BASE - default 0x10070000 + default 0x10090000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC + default 0x10070000 if SOC_NPCX7M7FC config CROS_EC_RAM_BASE default 0x200c0000 @@ -67,14 +29,17 @@ config CROS_EC_RAM_SIZE default 0x0000f800 config FLASH_SIZE - default 512 + default 1024 if SOC_NPCX7M6FB + default 512 if SOC_NPCX7M6FC || SOC_NPCX7M7FC config CROS_EC_RO_MEM_OFF default 0x0 -# Image size limited by 1/2 Flash size (256 KiB) +# NPCX796FB/NPCX796FC: Image size limited by code RAM size (192 KiB) +# NPCX797FC: Image size limited by 1/2 Flash size (256 KiB) config CROS_EC_RO_SIZE - default 0x40000 + default 0x30000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC + default 0x40000 if SOC_NPCX7M7FC # RW firmware in program memory - Identical to RO, only one image loaded at a # time. @@ -82,8 +47,7 @@ config CROS_EC_RW_MEM_OFF default 0x0 config CROS_EC_RW_SIZE - default 0x40000 - -endif # SOC_NPCX7M7FC + default 0x30000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC + default 0x40000 if SOC_NPCX7M7FC endif # SOC_SERIES_NPCX7 diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 index cc41bb408f..5fd1fbd308 100644 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 +++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 @@ -8,15 +8,15 @@ if SOC_SERIES_NPCX9 -if SOC_NPCX9M3F - # # NPCX993F: 512 KiB Flash, 256 KiB code RAM, 64 KiB data RAM +# NPCX996F: 512 KiB Flash, 192 KiB code RAM, 64 KiB data RAM # -# Code RAM base for NPCX993F +# Code RAM base for NPCX9 series config CROS_EC_PROGRAM_MEMORY_BASE - default 0x10080000 + default 0x10080000 if SOC_NPCX9M3F + default 0x10090000 if SOC_NPCX9M6F config CROS_EC_RAM_BASE default 0x200c0000 @@ -33,16 +33,19 @@ config FLASH_SIZE config CROS_EC_RO_MEM_OFF default 0x0 -# Image size limited by 1/2 Flash size (256 KiB) and code RAM size (256 KiB) +# NPCX993F: Image size limited by 1/2 Flash size (256 KiB) and +# code RAM size (256 KiB) +# NPCX996F: Image size limited by code RAM size (192 KiB) + config CROS_EC_RO_SIZE - default 0x40000 + default 0x40000 if SOC_NPCX9M3F + default 0x30000 if SOC_NPCX9M6F config CROS_EC_RW_MEM_OFF - default 0x40000 + default 0x0 config CROS_EC_RW_SIZE - default 0x40000 - -endif # SOC_NPCX9M3F + default 0x40000 if SOC_NPCX9M3F + default 0x30000 if SOC_NPCX9M6F endif # SOC_SERIES_NPCX9 |