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authorJack Rosenthal <jrosenth@chromium.org>2021-01-11 16:12:16 -0700
committerCommit Bot <commit-bot@chromium.org>2021-01-12 17:05:29 +0000
commit32c9bfbe5cb5742a72576fb400f2b83268833130 (patch)
treea789ea9982dd040a8b7eafe2ff88921b644cc279 /zephyr/app/ec
parent49483cc7845de56db35c21669781ca6cfe1b7e49 (diff)
downloadchrome-ec-32c9bfbe5cb5742a72576fb400f2b83268833130.tar.gz
zephyr: copy zephyr-chrome/app directory to platform/ec
Previous Git history can be found here: https://chromium.googlesource.com/chromiumos/platform/zephyr-chrome/+/cc6e5d19939c03ac091b5e91d1a3b511ba99b68a/app/ BUG=b:177157241 BRANCH=none TEST=zmake testall Cq-Depend: chromium:2623408 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ib66a60b5404ed04e330721e96ab91e38ad97d2db Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2622901 Reviewed-by: Yuval Peress <peress@chromium.org>
Diffstat (limited to 'zephyr/app/ec')
-rw-r--r--zephyr/app/ec/CMakeLists.txt7
-rw-r--r--zephyr/app/ec/Kconfig96
-rw-r--r--zephyr/app/ec/main.c39
-rw-r--r--zephyr/app/ec/soc/Kconfig50
4 files changed, 192 insertions, 0 deletions
diff --git a/zephyr/app/ec/CMakeLists.txt b/zephyr/app/ec/CMakeLists.txt
new file mode 100644
index 0000000000..608d2343fb
--- /dev/null
+++ b/zephyr/app/ec/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if(NOT DEFINED CONFIG_ZTEST)
+ target_sources(app PRIVATE main.c)
+endif()
diff --git a/zephyr/app/ec/Kconfig b/zephyr/app/ec/Kconfig
new file mode 100644
index 0000000000..22519a20fa
--- /dev/null
+++ b/zephyr/app/ec/Kconfig
@@ -0,0 +1,96 @@
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig CROS_EC
+ bool "Chromium OS EC app"
+ imply SHELL
+ imply PRINTK
+ help
+ Enable the common Chromium OS EC application. This prints a message,
+ starts the EC tasks and sets up any drivers that are needed.
+
+ This depends on PLATFORM_EC at present, since without the shimmed
+ tasks, almost nothing can operate.
+
+if CROS_EC
+
+rsource "soc/Kconfig"
+
+choice
+ prompt "Chromium OS EC firmware section"
+
+config CROS_EC_RO
+ bool "This build is will be for the RO copy of the EC"
+ help
+ This build will be used to produce a copy for the read-only
+ section of the EC firmware.
+
+config CROS_EC_RW
+ bool "This build is will be for the RW copy of the EC"
+ help
+ This build will be used to produce a copy for the read-write
+ section of the EC firmware.
+
+endchoice
+
+config CROS_EC_ACTIVE_COPY
+ string
+ default "RO" if CROS_EC_RO
+ default "RW" if CROS_EC_RW
+ help
+ When the active copy name is output to a console, this
+ string will be displayed.
+
+config CROS_EC_RAM_SIZE
+ hex "The total available RAM size."
+ help
+ This value describes the total available RAM size for the chip.
+
+config CROS_EC_DATA_RAM_SIZE
+ hex "The total available RAM size for data."
+ help
+ This value describes the total available RAM size for data on the chip.
+
+config CROS_EC_RAM_BASE
+ hex "Base address of RAM for the chip."
+ help
+ Base address of RAM for the chip.
+
+config CROS_EC_PROGRAM_MEMORY_BASE
+ hex "The base address of the program memory region."
+ help
+ This will be used (among other things) to calculate the current PC's
+ offset within the program memory.
+
+config CROS_EC_RO_MEM_OFF
+ hex "The RO region's offset."
+ help
+ This will be used to determine if the current PC is in the RO section.
+
+config CROS_EC_RO_SIZE
+ hex "The size of the RO region."
+ help
+ This will be used (along with SYSTEM_RO_MEM_OFF) to determine if the
+ current PC is in the RO section.
+
+config CROS_EC_RW_MEM_OFF
+ hex "The RW region's offset."
+ help
+ This will be used to determine if the current PC is in the RW section.
+
+config CROS_EC_RW_SIZE
+ hex "The size of the RW region."
+ help
+ This will be used (along with SYSTEM_RW_MEM_OFF) to determine if the
+ current PC is in the RW section.
+
+config SHIMMED_TASKS
+ bool "Add support for shimming in platform/ec tasks as Zephyr threads"
+ help
+ When this option is enabled, a shimmed_tasks.h header with the
+ CROS_EC_TASK_LIST defined needs to be included for the project to
+ build. The CROS_EC_TASK_LIST defines a list of CROS_EC_TASK that
+ should be shimmed in.
+
+endif # CROS_EC
diff --git a/zephyr/app/ec/main.c b/zephyr/app/ec/main.c
new file mode 100644
index 0000000000..d8296e6409
--- /dev/null
+++ b/zephyr/app/ec/main.c
@@ -0,0 +1,39 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <sys/printk.h>
+#include <zephyr.h>
+
+#include "ec_tasks.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "zephyr_espi_shim.h"
+
+void main(void)
+{
+ printk("Hello from a Chrome EC!\n");
+ printk(" BOARD=%s\n", CONFIG_BOARD);
+ printk(" ACTIVE_COPY=%s\n", CONFIG_CROS_EC_ACTIVE_COPY);
+
+ if (IS_ENABLED(HAS_TASK_KEYSCAN)) {
+ keyboard_scan_init();
+ }
+
+ if (IS_ENABLED(CONFIG_PLATFORM_EC_ESPI)) {
+ if (zephyr_shim_setup_espi() < 0) {
+ printk("Failed to init eSPI!\n");
+ }
+ }
+
+ /* Call init hooks before main tasks start */
+ if (IS_ENABLED(CONFIG_PLATFORM_EC_HOOKS)) {
+ hook_notify(HOOK_INIT);
+ }
+
+ /* Start the EC tasks after performing all main initialization */
+ if (IS_ENABLED(CONFIG_SHIMMED_TASKS)) {
+ start_ec_tasks();
+ }
+}
diff --git a/zephyr/app/ec/soc/Kconfig b/zephyr/app/ec/soc/Kconfig
new file mode 100644
index 0000000000..75577120ad
--- /dev/null
+++ b/zephyr/app/ec/soc/Kconfig
@@ -0,0 +1,50 @@
+menuconfig AP
+ bool "Enable AP SoC support code"
+ default y
+ help
+ This device has an application processor (AP) on-board and
+ support code should be enabled.
+
+if AP
+
+choice
+ prompt "SoC chipset generation"
+
+config AP_X86_INTEL_TGL
+ bool "AP is TGL chipset"
+ select AP_X86_INTEL
+ help
+ The application processor is Intel Tiger Lake (TGL) chipset.
+
+config AP_X86_INTEL_ADL
+ bool "AP is ADL chipset"
+ select AP_X86_INTEL
+ help
+ The application processor is Intel Alder Lake (ADL) chipset.
+
+endchoice
+
+# Invisible meta-symbols generated by the selected chipset.
+config AP_X86_INTEL
+ bool
+ select AP_X86
+ help
+ The application processor (AP) is an Intel SoC.
+
+config AP_X86_AMD
+ bool
+ select AP_X86
+ help
+ The application processor (AP) is an AMD SoC.
+
+config AP_X86
+ bool
+ help
+ The application processor (AP) is X86-like.
+
+config AP_ARM
+ bool
+ help
+ The application processor (AP) is ARM-like.
+
+endif # AP