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| author | Dino Li <Dino.Li@ite.com.tw> | 2021-08-16 14:02:13 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-08-17 04:49:53 +0000 |
| commit | a46efa226904918b2144f3d92721b78e10adee3d (patch) | |
| tree | 6b49a826b3122028df1e76279b6a3ec8270b7feb /zephyr/app | |
| parent | eef0516b7cd563e6419520ac4ded110b00c17732 (diff) | |
| download | chrome-ec-a46efa226904918b2144f3d92721b78e10adee3d.tar.gz | |
zephyr: it8xxx2: use half space (512KB) from flash
This saved about 3 seconds erasing time while running software sync.
This also pull configurations of flash/memory layout to chip level.
BRANCH=none
BUG=b:195954913
TEST=software sync successfully.
(without erase timeout patch of depthcharge)
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ia7fa08fdf6bdde4c47ca8d852f8eeaa83f39dae5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3097250
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Diffstat (limited to 'zephyr/app')
| -rw-r--r-- | zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 index 1d60630027..dab9e6b8b2 100644 --- a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 +++ b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 @@ -4,6 +4,37 @@ if SOC_FAMILY_RISCV_ITE +# Code RAM base for IT8XXX2 +config CROS_EC_PROGRAM_MEMORY_BASE + default 0x80000000 + +# The total RAM size of IT8xxx2 is 60 KB. +# The first 4KB block be always reserved for ram code functions, +# so the total available RAM size will be 56KB. +config CROS_EC_RAM_BASE + default 0x80101000 + +config CROS_EC_DATA_RAM_SIZE + default 0x0000e000 + +config CROS_EC_RAM_SIZE + default 0x0000e000 + +# The 512KB flash space layout are as the below: +# - RO image starts at the beginning of flash. +# - RW image starts at the second half of flash. +config CROS_EC_RO_MEM_OFF + default 0x0 + +config CROS_EC_RO_SIZE + default 0x40000 + +config CROS_EC_RW_MEM_OFF + default 0x40000 + +config CROS_EC_RW_SIZE + default 0x40000 + config FLASH_LOAD_OFFSET default CROS_EC_RW_MEM_OFF if CROS_EC_RW |