zephyr: npcx9: Move chip specific configs to Kconfig.npcx9

Similar to Kconfig.npcx7, move the NPCX9 specific configs to this file.
And create Kconfig.npcx which contains the configs shared by all NPCX
chipsets.

This CL just moves the configs and doesn't modify the values.

BRANCH=None
BUG=b:192253134
TEST=Built the brya and lazor images. Booted the lazor image on
Lazor board.

Change-Id: I68a126e0102d3be49c2fb1620da64ba371d1404e
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3029001
Reviewed-by: Keith Short <keithshort@chromium.org>

4 files changed, 89 insertions, 36 deletions

diff --git a/zephyr/app/ec/Kconfig b/zephyr/app/ec/Kconfig
index 7507f49e83..9f533aeac8 100644
--- a/zephyr/app/ec/Kconfig
+++ b/zephyr/app/ec/Kconfig
@@ -17,12 +17,7 @@ menuconfig CROS_EC
 if CROS_EC
 
 rsource "soc/Kconfig"
-
-if SOC_SERIES_NPCX7
-
-rsource "chip/Kconfig.npcx7"
-
-endif # SOC_SERIES_NPCX7
+rsource "chip/Kconfig.*"
 
 config LTO
 	bool "Link Time Optimization (LTO)"
diff --git a/zephyr/app/ec/chip/Kconfig.npcx b/zephyr/app/ec/chip/Kconfig.npcx
new file mode 100644
index 0000000000..b4a7c36a3d
--- /dev/null
+++ b/zephyr/app/ec/chip/Kconfig.npcx
@@ -0,0 +1,37 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+#
+# This file defines the default config values shared by all NPCX chipsets
+#
+
+if SOC_FAMILY_NPCX
+
+# ADC
+# The resolution and oversamplig values are fixed by the NPCX ADC driver
+config PLATFORM_EC_ADC_RESOLUTION
+	default 10
+
+config PLATFORM_EC_ADC_OVERSAMPLING
+	default 0
+
+# Set the system clock to 15MHz.
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 15000000
+
+if WATCHDOG
+
+# Set the delay time for printing panic data.
+# 1 cycle is about 32ms. 500ms is about 16 cycles.
+config WDT_NPCX_DELAY_CYCLES
+	default 16
+
+endif # WATCHDOG
+
+# The maximum supported time the NPCX can spend in deep-sleep with instant
+# wake is 200 ms, so the hook tick interval is set to match.
+config CROS_EC_HOOK_TICK_INTERVAL
+	default 200000
+
+endif # SOC_FAMILY_NPCX
diff --git a/zephyr/app/ec/chip/Kconfig.npcx7 b/zephyr/app/ec/chip/Kconfig.npcx7
index c843bd795f..26b36509ad 100644
--- a/zephyr/app/ec/chip/Kconfig.npcx7
+++ b/zephyr/app/ec/chip/Kconfig.npcx7
@@ -6,6 +6,8 @@
 # This file defines the correct defaults when using the NPCX7 series chipset
 #
 
+if SOC_SERIES_NPCX7
+
 if SOC_NPCX7M6FC
 
 #
@@ -84,33 +86,4 @@ config CROS_EC_RW_SIZE
 
 endif # SOC_NPCX7M7FC
 
-#
-# Default config values shared by all NPCX7 devices
-#
-
-# ADC
-# The resolution and oversamplig values are fixed by the NPCX ADC driver
-config PLATFORM_EC_ADC_RESOLUTION
-	default 10
-
-config PLATFORM_EC_ADC_OVERSAMPLING
-	default 0
-
-# Set the system clock to 15MHz.
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 15000000
-
-if WATCHDOG
-
-# Set the delay time for printing panic data.
-# 1 cycle is about 32ms. 500ms is about 16 cycles.
-config WDT_NPCX_DELAY_CYCLES
-	default 16
-
-endif # WATCHDOG
-
-# The maximum supported time the NPCX can spend in deep-sleep with instant
-# wake is 200 ms, so the hook tick interval is set to match.
-config CROS_EC_HOOK_TICK_INTERVAL
-	default 200000
-
+endif # SOC_SERIES_NPCX7
diff --git a/zephyr/app/ec/chip/Kconfig.npcx9 b/zephyr/app/ec/chip/Kconfig.npcx9
new file mode 100644
index 0000000000..cc41bb408f
--- /dev/null
+++ b/zephyr/app/ec/chip/Kconfig.npcx9
@@ -0,0 +1,48 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+#
+# This file defines the correct defaults when using the NPCX9 series chipset
+#
+
+if SOC_SERIES_NPCX9
+
+if SOC_NPCX9M3F
+
+#
+# NPCX993F: 512 KiB Flash, 256 KiB code RAM, 64 KiB data RAM
+#
+
+# Code RAM base for NPCX993F
+config CROS_EC_PROGRAM_MEMORY_BASE
+	default 0x10080000
+
+config CROS_EC_RAM_BASE
+	default 0x200c0000
+
+config CROS_EC_DATA_RAM_SIZE
+	default 0x0000f800
+
+config CROS_EC_RAM_SIZE
+	default 0x0000f800
+
+config FLASH_SIZE
+	default 512
+
+config CROS_EC_RO_MEM_OFF
+	default 0x0
+
+# Image size limited by 1/2 Flash size (256 KiB) and code RAM size (256 KiB)
+config CROS_EC_RO_SIZE
+	default 0x40000
+
+config CROS_EC_RW_MEM_OFF
+	default 0x40000
+
+config CROS_EC_RW_SIZE
+	default 0x40000
+
+endif # SOC_NPCX9M3F
+
+endif # SOC_SERIES_NPCX9