diff options
| author | Jun Lin <CHLin56@nuvoton.com> | 2021-08-12 15:13:02 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-08-17 03:25:20 +0000 |
| commit | 693569ad6b75ef632c2089ae64b57eead73d8383 (patch) | |
| tree | e405c9cbc6826b4b38497cc0eac713c66fc3721c /zephyr/boards/arm/npcx_evb/npcx_evb.dtsi | |
| parent | 23b055bf5e7d5dd073de800ccaa9bbb165472054 (diff) | |
| download | chrome-ec-693569ad6b75ef632c2089ae64b57eead73d8383.tar.gz | |
zephyr: npcx_evb: add the PSL hibernate wake-up pins
Add PSL_IN1/PSL_IN2/PSL_IN3 as the hibernate wakeup pins. Also map the
non-PSL (low power RAM) hibernate wakeup source to the same pads.
(i.e. GPIOD2/GPIO00/GPIO01.) Then we can use either PSL hibernate mode
(CONFIG_PLATFORM_EC_HIBERNATE_PSL=y) or non-PSL hibernate mode
(CONFIG_PLATFORM_EC_HIBERNATE_PSL=n) on the EVB.
BUG=none
BRANCH=none
TEST=pass "zmake testall"
TEST='hibernate' & wake-up ec by those wakeup pins.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I4175bdabee138c7bac25f8b43774268ae336d989
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3089083
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Diffstat (limited to 'zephyr/boards/arm/npcx_evb/npcx_evb.dtsi')
| -rw-r--r-- | zephyr/boards/arm/npcx_evb/npcx_evb.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi index e3fb482659..51f40d6594 100644 --- a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi +++ b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi @@ -75,6 +75,11 @@ channel = <4>; }; }; + + vsby-psl-in-list { + /* Use PSL_IN1/2/3 as detection pins from hibernate mode */ + psl-in-pads = <&psl_in1 &psl_in2 &psl_in3>; + }; }; &i2c0_0 { @@ -106,6 +111,17 @@ status = "okay"; }; +/* Power switch logic input pads */ +&psl_in1 { + flag = <NPCX_PSL_FALLING_EDGE>; +}; +&psl_in2 { + flag = <NPCX_PSL_FALLING_EDGE>; +}; +&psl_in3 { + flag = <NPCX_PSL_RISING_EDGE>; +}; + &cros_kb_raw { status = "okay"; pinctrl-0 = <&alt7_no_ksi0_sl |