zephyr: move all the boards directories under zephyr/boards

Move all the boards directories together under zephyr/boards from
their scattered locations under projects/.

This is the first step towards de-coupling the concept of a Zephyr
board from baseboard/board/model, as it currently is.  Further work
will be required to actually unify these directories and delete the
baseboard-specific names from our tree.

BUG=b:193814903
BRANCH=none
TEST=zmake testall

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I33a344af6890b2c2c54f1e91f0f0fa85caaf19d3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3035222
Commit-Queue: Yuval Peress <peress@chromium.org>
Reviewed-by: Yuval Peress <peress@chromium.org>

21 files changed, 1362 insertions, 0 deletions

diff --git a/zephyr/boards/arm/brya/Kconfig.board b/zephyr/boards/arm/brya/Kconfig.board
new file mode 100644
index 0000000000..8add483941
--- /dev/null
+++ b/zephyr/boards/arm/brya/Kconfig.board
@@ -0,0 +1,15 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# "BOARD" below refers to a Zephyr board, which does not have a 1:1
+# mapping with the Chrome OS concept of a board.  By Zephyr's
+# conventions, we'll still call it "BOARD_*" to make this more
+# applicable to be upstreamed, even though this code is shared by all
+# projects using Brya baseboard.
+config BOARD_BRYA
+	bool "Google Brya Baseboard"
+	depends on SOC_NPCX9M3F
+	# NPCX doesn't actually have enough ram for coverage, but this will
+	# allow generating initial 0 line coverage.
+	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/brya/Kconfig.defconfig b/zephyr/boards/arm/brya/Kconfig.defconfig
new file mode 100644
index 0000000000..e4de179311
--- /dev/null
+++ b/zephyr/boards/arm/brya/Kconfig.defconfig
@@ -0,0 +1,10 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if BOARD_BRYA
+
+config BOARD
+	default "brya"
+
+endif # BOARD_BRYA
diff --git a/zephyr/boards/arm/brya/board.cmake b/zephyr/boards/arm/brya/board.cmake
new file mode 100644
index 0000000000..67ade59f57
--- /dev/null
+++ b/zephyr/boards/arm/brya/board.cmake
@@ -0,0 +1,6 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin)
+
diff --git a/zephyr/boards/arm/brya/brya.dts b/zephyr/boards/arm/brya/brya.dts
new file mode 100644
index 0000000000..a0680342af
--- /dev/null
+++ b/zephyr/boards/arm/brya/brya.dts
@@ -0,0 +1,156 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/nuvoton/npcx9.dtsi>
+#include <dt-bindings/gpio_defines.h>
+#include <nuvoton/npcx9m3f.dtsi>
+
+/ {
+	model = "Google Brya Baseboard";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,flash = &flash0;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+		i2c_sensor: sensor {
+			i2c-port = <&i2c0_0>;
+			enum-name = "I2C_PORT_SENSOR";
+			label = "SENSOR";
+		};
+		tcpc0_2 {
+			i2c-port = <&i2c1_0>;
+			enum-name = "I2C_PORT_USB_C0_C2_TCPC";
+			label = "TCPC0,2";
+		};
+		tcpc1 {
+			i2c-port = <&i2c4_1>;
+			enum-name = "I2C_PORT_USB_C1_TCPC";
+			label = "TCPC1";
+		};
+		ppc0_2 {
+			i2c-port = <&i2c2_0>;
+			enum-name = "I2C_PORT_USB_C0_C2_PPC";
+			label = "PPC0,2";
+		};
+		ppc1 {
+			i2c-port = <&i2c6_1>;
+			enum-name = "I2C_PORT_USB_C1_PPC";
+			label = "PPC1";
+		};
+		retimer0_2 {
+			i2c-port = <&i2c3_0>;
+			enum-name = "I2C_PORT_USB_C0_C2_MUX";
+			label = "RETIMER0,2";
+		};
+		battery {
+			i2c-port = <&i2c5_0>;
+			enum-name = "I2C_PORT_BATTERY";
+			label = "BATTERY";
+		};
+		eeprom {
+			i2c-port = <&i2c7_0>;
+			enum-name = "I2C_PORT_EEPROM";
+			label = "EEPROM";
+		};
+		charger {
+			i2c-port = <&i2c7_0>;
+			enum-name = "I2C_PORT_CHARGER";
+			label = "EEPROM";
+		};
+	};
+
+	named-pwms {
+		compatible = "named-pwms";
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+	};
+
+	def-lvol-io-list {
+		compatible = "nuvoton,npcx-lvolctrl-def";
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>;
+};
+
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c1_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c2_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c3_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c4_1 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c5_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&i2c6_1 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c7_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&alt7_no_ksi0_sl
+		     &alt7_no_ksi1_sl
+		     &alt7_no_ksi2_sl
+		     &alt7_no_ksi3_sl
+		     &alt7_no_ksi4_sl
+		     &alt7_no_ksi5_sl
+		     &alt7_no_ksi6_sl
+		     &alt7_no_ksi7_sl
+		     &alt8_no_kso00_sl
+		     &alt8_no_kso01_sl
+		     &alt8_no_kso03_sl
+		     &alt8_no_kso04_sl
+		     &alt8_no_kso05_sl
+		     &alt8_no_kso06_sl
+		     &alt8_no_kso07_sl
+		     &alt9_no_kso08_sl
+		     &alt9_no_kso09_sl
+		     &alt9_no_kso10_sl
+		     &alt9_no_kso11_sl
+		     &alt9_no_kso12_sl
+		     &alt9_no_kso13_sl
+		     &alt9_no_kso14_sl
+		     >;
+};
diff --git a/zephyr/boards/arm/brya/brya_defconfig b/zephyr/boards/arm/brya/brya_defconfig
new file mode 100644
index 0000000000..4abece1033
--- /dev/null
+++ b/zephyr/boards/arm/brya/brya_defconfig
@@ -0,0 +1,37 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_NPCX9=y
+
+# Platform Configuration
+CONFIG_SOC_NPCX9M3F=y
+CONFIG_BOARD_BRYA=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinmux Driver
+CONFIG_PINMUX=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# Power Management
+CONFIG_SOC_POWER_MANAGEMENT=y
+CONFIG_PM=y
+CONFIG_PM_POLICY_APP=y
+CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
+CONFIG_SOC_POWER_MANAGEMENT_TRACE=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
diff --git a/zephyr/boards/arm/kohaku/Kconfig.board b/zephyr/boards/arm/kohaku/Kconfig.board
new file mode 100644
index 0000000000..c1a1718847
--- /dev/null
+++ b/zephyr/boards/arm/kohaku/Kconfig.board
@@ -0,0 +1,10 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_KOHAKU
+	bool "Google Kohaku EC"
+	depends on SOC_NPCX7M6FC
+	# NPCX doesn't actually have enough ram for coverage, but this will
+	# allow generating initial 0 line coverage.
+	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/kohaku/Kconfig.defconfig b/zephyr/boards/arm/kohaku/Kconfig.defconfig
new file mode 100644
index 0000000000..83b97d8ef7
--- /dev/null
+++ b/zephyr/boards/arm/kohaku/Kconfig.defconfig
@@ -0,0 +1,10 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if BOARD_KOHAKU
+
+config BOARD
+	default "kohaku"
+
+endif # BOARD_KOHAKU
diff --git a/zephyr/boards/arm/kohaku/board.cmake b/zephyr/boards/arm/kohaku/board.cmake
new file mode 100644
index 0000000000..a204305534
--- /dev/null
+++ b/zephyr/boards/arm/kohaku/board.cmake
@@ -0,0 +1,5 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin)
diff --git a/zephyr/boards/arm/kohaku/kohaku.dts b/zephyr/boards/arm/kohaku/kohaku.dts
new file mode 100644
index 0000000000..1670dcc0f2
--- /dev/null
+++ b/zephyr/boards/arm/kohaku/kohaku.dts
@@ -0,0 +1,394 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/nuvoton/npcx7.dtsi>
+#include <dt-bindings/gpio_defines.h>
+#include <nuvoton/npcx7m6fc.dtsi>
+
+/ {
+	model = "Google Kohaku EC";
+
+	aliases {
+		i2c-0 = &i2c0_0;
+		i2c-1 = &i2c1_0;
+		i2c-2 = &i2c2_0;
+		i2c-3 = &i2c3_0;
+		i2c-5 = &i2c5_0;
+		i2c-7 = &i2c7_0;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,flash = &flash0;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+			label = "LID_OPEN";
+		};
+		wp_l {
+			gpios = <&gpioa 1 GPIO_INPUT>;
+			enum-name = "GPIO_WP_L";
+			label = "WP_L";
+		};
+		power_button_l {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+			label = "POWER_BUTTON_L";
+		};
+		acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+			label = "ACOK_OD";
+		};
+		slp_s0_l {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S0_L";
+			label = "SLP_S0_L";
+		};
+		slp_s3_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S3_L";
+			label = "SLP_S3_L";
+		};
+		slp_s4_l {
+			gpios = <&gpiod 4 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S4_L";
+			label = "SLP_S4_L";
+		};
+		pg_ec_rsmrst_l {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+			enum-name = "GPIO_RSMRST_L_PGOOD";
+			label = "PG_EC_RSMRST_L";
+		};
+		pg_ec_all_sys_pwrgd {
+			gpios = <&gpiof 4 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
+			label = "PG_EC_ALL_SYS_PWRGD";
+		};
+		pp5000_a_pg_od {
+			gpios = <&gpiod 7 GPIO_INPUT>;
+			enum-name = "GPIO_PP5000_A_PG_OD";
+			label = "PP5000_A_PG_OD";
+		};
+		base_sixaxis_int_l {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+			label = "BASE_SIXAXIS_INT_L";
+		};
+		wfcam_vsync {
+			gpios = <&gpiob 7 GPIO_INPUT>;
+			label = "WFCAM_VSYNC";
+		};
+		tcs3400_int_odl {
+			gpios = <&gpio7 2 GPIO_INPUT>;
+			label = "TCS3400_INT_ODL";
+		};
+		usb_c0_ppc_int_odl {
+			gpios = <&gpioe 0 GPIO_INPUT>;
+			label = "USB_C0_PPC_INT_ODL";
+		};
+		usb_c1_ppc_int_odl {
+			gpios = <&gpioa 2 GPIO_INPUT>;
+			label = "USB_C1_PPC_INT_ODL";
+		};
+		usb_c0_tcpc_int_odl {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+			label = "USB_C0_TCPC_INT_ODL";
+		};
+		usb_c1_tcpc_int_odl {
+			gpios = <&gpiof 5 GPIO_INPUT>;
+			label = "USB_C1_TCPC_INT_ODL";
+		};
+		usb_c0_bc12_int_odl {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+			label = "USB_C0_BC12_INT_ODL";
+		};
+		usb_c1_bc12_int_odl {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+			label = "USB_C1_BC12_INT_ODL";
+		};
+		ec_voldn_btn_odl {
+			gpios = <&gpio9 3 (GPIO_INPUT | GPIO_PULL_UP)>;
+			label = "EC_VOLDN_BTN_ODL";
+		};
+		ec_volup_btn_odl {
+			gpios = <&gpio7 5 (GPIO_INPUT | GPIO_PULL_UP)>;
+			label = "EC_VOLUP_BTN_ODL";
+		};
+		sys_reset_l {
+			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_SYS_RESET_L";
+			label = "SYS_RESET_L";
+		};
+		entering_rw {
+			gpios = <&gpioe 3 GPIO_OUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+			label = "ENTERING_RW";
+		};
+		pch_wake_l {
+			gpios = <&gpio7 4 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_PCH_WAKE_ODL";
+			label = "PCH_WAKE_L";
+		};
+		pch_pwrbtn_l {
+			gpios = <&gpioc 1 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+			label = "PCH_PWRBTN_L";
+		};
+		en_pp5000_a {
+			gpios = <&gpioa 4 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EN_PP5000_A";
+			label = "EN_PP5000_A";
+		};
+		en_pp5000 {
+			gpios = <&gpioa 4 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EN_PP5000";
+			label = "EN_PP5000";
+		};
+		gpio_edp_bklten_od {
+			gpios = <&gpiod 3 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+			label = "EDP_BKLTEN_OD";
+		};
+		en_a_rails {
+			gpios = <&gpioa 3 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EN_A_RAILS";
+			label = "EN_A_RAILS";
+		};
+		ec_pch_rsmrst_l {
+			gpios = <&gpioa 6 GPIO_OUT_LOW>;
+			enum-name = "GPIO_PCH_RSMRST_L";
+			label = "EC_PCH_RSMRST_L";
+		};
+		ec_prochot_odl {
+			gpios = <&gpio6 3 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_CPU_PROCHOT";
+			label = "EC_PROCHOT_ODL";
+		};
+		ec_prochot_in_od {
+			gpios = <&gpio3 4 GPIO_INPUT>;
+			label = "EC_PROCHOT_IN_OD";
+		};
+		ec_pch_sys_pwrok {
+			gpios = <&gpio3 7 GPIO_OUT_LOW>;
+			enum-name = "GPIO_PCH_SYS_PWROK";
+			label = "EC_PCH_SYS_PWROK";
+		};
+		cpu_c10_gate_l {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+			label = "CPU_C10_GATE_L";
+		};
+		ec_int_l {
+			gpios = <&gpio7 0 GPIO_ODR_HIGH>;
+			label = "EC_INT_L";
+		};
+		ec_rst_odl {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+			label = "EC_RST_ODL";
+		};
+		usb_c_oc_odl {
+			gpios = <&gpiob 1 GPIO_ODR_HIGH>;
+			label = "USB_C_OC_ODL";
+		};
+		usb_c0_tcpc_rst_odl {
+			gpios = <&gpio9 7 GPIO_ODR_HIGH>;
+			label = "USB_C0_TCPC_RST_ODL";
+		};
+		usb_c1_tcpc_rst_odl {
+			gpios = <&gpio3 2 GPIO_ODR_HIGH>;
+			label = "USB_C1_TCPC_RST_ODL";
+		};
+		usb_c0_bc12_chg_det_l {
+			gpios = <&gpio6 0 GPIO_INPUT>;
+			label = "USB_C0_BC12_CHG_DET_L";
+		};
+		usb_c1_bc12_chg_det_l {
+			gpios = <&gpio9 6 GPIO_INPUT>;
+			label = "USB_C1_BC12_CHG_DET_L";
+		};
+		usb_c0_bc12_vbus_on {
+			gpios = <&gpio9 4 GPIO_OUT_LOW>;
+			label = "USB_C0_BC12_VBUS_ON";
+		};
+		usb_c1_bc12_vbus_on {
+			gpios = <&gpioc 6 GPIO_OUT_LOW>;
+			label = "USB_C1_BC12_VBUS_ON";
+		};
+		ec_batt_pres_odl {
+			gpios = <&gpioe 1 GPIO_INPUT>;
+			label = "EC_BATT_PRES_ODL";
+		};
+		led_1_l {
+			gpios = <&gpioc 4 GPIO_OUT_HIGH>;
+			label = "LED_1_L";
+		};
+		led_2_l {
+			gpios = <&gpioc 3 GPIO_OUT_HIGH>;
+			label = "LED_2_L";
+		};
+		led_3_l {
+			gpios = <&gpioc 2 GPIO_OUT_HIGH>;
+			label = "LED_3_L";
+		};
+		ec_kb_bl_en {
+			gpios = <&gpio8 6 GPIO_OUT_LOW>;
+			label = "EC_KB_BL_EN";
+		};
+		edp_bklten_od {
+			gpios = <&gpiod 3 GPIO_ODR_HIGH>;
+			label = "EDP_BKLTEN_OD";
+		};
+		lid_accel_int_l {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+			label = "LID_ACCEL_INT_L";
+		};
+		m2_sd_pln {
+			gpios = <&gpioa 0 (GPIO_INPUT | GPIO_PULL_UP)>;
+			label = "M2_SD_PLN";
+		};
+		imvp8_pe {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+			label = "IMVP8_PE";
+		};
+		i2c0_scl {
+			gpios = <&gpiob 5 GPIO_INPUT>;
+			label = "I2C0_SCL";
+		};
+		i2c0_sda {
+			gpios = <&gpiob 4 GPIO_INPUT>;
+			label = "I2C0_SDA";
+		};
+		i2c1_scl {
+			gpios = <&gpio9 0 GPIO_INPUT>;
+			label = "I2C1_SCL";
+		};
+		i2c1_sda {
+			gpios = <&gpio8 7 GPIO_INPUT>;
+			label = "I2C1_SDA";
+		};
+		i2c2_scl {
+			gpios = <&gpio9 2 GPIO_INPUT>;
+			label = "I2C2_SCL";
+		};
+		i2c2_sda {
+			gpios = <&gpio9 1 GPIO_INPUT>;
+			label = "I2C2_SDA";
+		};
+		i2c3_scl {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+			label = "I2C3_SCL";
+		};
+		i2c3_sda {
+			gpios = <&gpiod 0 GPIO_INPUT>;
+			label = "I2C3_SDA";
+		};
+		i2c5_scl {
+			gpios = <&gpio3 3 GPIO_INPUT>;
+			label = "I2C5_SCL";
+		};
+		i2c5_sda {
+			gpios = <&gpio3 6 GPIO_INPUT>;
+			label = "I2C5_SDA";
+		};
+		i2c7_scl {
+			gpios = <&gpiob 3 GPIO_INPUT>;
+			label = "I2C7_SCL";
+		};
+		i2c7_sda {
+			gpios = <&gpiob 2 GPIO_INPUT>;
+			label = "I2C7_SDA";
+		};
+		tp58 {
+			gpios = <&gpio0 4 (GPIO_INPUT | GPIO_PULL_UP)>;
+			label = "TP58";
+		};
+		tp73 {
+			gpios = <&gpio8 2 (GPIO_INPUT | GPIO_PULL_UP)>;
+			label = "TP73";
+		};
+		tp18 {
+			gpios = <&gpioc 0 (GPIO_INPUT | GPIO_PULL_UP)>;
+			label = "TP18";
+		};
+		tp54 {
+			gpios = <&gpio4 0 (GPIO_INPUT | GPIO_PULL_UP)>;
+			label = "TP54";
+		};
+		tp56 {
+			gpios = <&gpio6 1 (GPIO_INPUT | GPIO_PULL_UP)>;
+			label = "TP56";
+		};
+		tp57 {
+			gpios = <&gpio8 1 (GPIO_INPUT | GPIO_PULL_UP)>;
+			label = "TP57";
+		};
+		tp55 {
+			gpios = <&gpio7 3 (GPIO_INPUT | GPIO_PULL_UP)>;
+			label = "TP55";
+		};
+		tp59 {
+			gpios = <&gpiob 0 (GPIO_INPUT | GPIO_PULL_UP)>;
+			label = "TP59";
+		};
+		kbd_kso2 {
+			gpios = <&gpio1 7 GPIO_OUT_LOW>;
+			label = "KBD_KSO2";
+		};
+	};
+
+	def-lvol-io-list {
+		compatible = "nuvoton,npcx-lvolctrl-def";
+		lvol-io-pads = <&lvol_iob4 &lvol_iob5 /* I2C_SDA0 & SCL0 */
+		                &lvol_io50>;          /* GPIO50 */
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */
+};
+
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c1_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c2_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c3_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&i2c5_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&i2c7_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
diff --git a/zephyr/boards/arm/kohaku/kohaku.yaml b/zephyr/boards/arm/kohaku/kohaku.yaml
new file mode 100644
index 0000000000..48cc85e7df
--- /dev/null
+++ b/zephyr/boards/arm/kohaku/kohaku.yaml
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2020 Google LLC.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: kohaku
+name: "Google Kohaku (Samsung Galaxy Chromebook) Embedded Controller"
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 64
+flash: 512
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
diff --git a/zephyr/boards/arm/kohaku/kohaku_defconfig b/zephyr/boards/arm/kohaku/kohaku_defconfig
new file mode 100644
index 0000000000..3235c6bc19
--- /dev/null
+++ b/zephyr/boards/arm/kohaku/kohaku_defconfig
@@ -0,0 +1,30 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_NPCX7=y
+CONFIG_SOC_NPCX7M6FC=y
+
+# Platform Configuration
+CONFIG_BOARD_KOHAKU=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinmux Driver
+CONFIG_PINMUX=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
diff --git a/zephyr/boards/arm/trogdor/Kconfig.board b/zephyr/boards/arm/trogdor/Kconfig.board
new file mode 100644
index 0000000000..4bfa4e50ac
--- /dev/null
+++ b/zephyr/boards/arm/trogdor/Kconfig.board
@@ -0,0 +1,15 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# "BOARD" below refers to a Zephyr board, which does not have a 1:1
+# mapping with the Chrome OS concept of a board.  By Zephyr's
+# conventions, we'll still call it "BOARD_*" to make this more
+# applicable to be upstreamed, even though this code is shared by all
+# projects using Trogdor baseboard.
+config BOARD_TROGDOR
+	bool "Google Trogdor Baseboard"
+	depends on SOC_NPCX7M7FC
+	# NPCX doesn't actually have enough ram for coverage, but this will
+	# allow generating initial 0 line coverage.
+	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/trogdor/Kconfig.defconfig b/zephyr/boards/arm/trogdor/Kconfig.defconfig
new file mode 100644
index 0000000000..bfd2e43bbf
--- /dev/null
+++ b/zephyr/boards/arm/trogdor/Kconfig.defconfig
@@ -0,0 +1,10 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if BOARD_TROGDOR
+
+config BOARD
+	default "trogdor"
+
+endif # BOARD_TROGDOR
diff --git a/zephyr/boards/arm/trogdor/board.cmake b/zephyr/boards/arm/trogdor/board.cmake
new file mode 100644
index 0000000000..a204305534
--- /dev/null
+++ b/zephyr/boards/arm/trogdor/board.cmake
@@ -0,0 +1,5 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin)
diff --git a/zephyr/boards/arm/trogdor/trogdor.dts b/zephyr/boards/arm/trogdor/trogdor.dts
new file mode 100644
index 0000000000..4bfbaca14d
--- /dev/null
+++ b/zephyr/boards/arm/trogdor/trogdor.dts
@@ -0,0 +1,247 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/nuvoton/npcx7.dtsi>
+#include <dt-bindings/adc/adc.h>
+#include <dt-bindings/gpio_defines.h>
+#include <dt-bindings/wake_mask_event_defines.h>
+#include <nuvoton/npcx7m7fc.dtsi>
+
+/ {
+	model = "Google Trogdor Baseboard";
+
+	aliases {
+		i2c-0 = &i2c0_0;
+		i2c-1 = &i2c1_0;
+		i2c-2 = &i2c2_0;
+		i2c-3 = &i2c3_0;
+		i2c-5 = &i2c5_0;
+		i2c-7 = &i2c7_0;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,flash = &flash0;
+		cros,rtc = &mtc;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+
+		disabled = "hostcmd";
+	};
+
+	ec-mkbp-host-event-wakeup-mask {
+		compatible = "ec-wake-mask-event";
+		wakeup-mask = <(HOST_EVENT_LID_OPEN | \
+				HOST_EVENT_POWER_BUTTON | \
+				HOST_EVENT_AC_CONNECTED | \
+				HOST_EVENT_AC_DISCONNECTED | \
+				HOST_EVENT_HANG_DETECT | \
+				HOST_EVENT_RTC | \
+				HOST_EVENT_MODE_CHANGE | \
+				HOST_EVENT_DEVICE)>;
+	};
+
+	ec-mkbp-event-wakeup-mask {
+		compatible = "ec-wake-mask-event";
+		wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | \
+				MKBP_EVENT_HOST_EVENT | \
+				MKBP_EVENT_SENSOR_FIFO)>;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		power {
+			i2c-port = <&i2c0_0>;
+			enum-name = "I2C_PORT_POWER";
+			label = "POWER";
+		};
+		battery {
+			i2c-port = <&i2c0_0>;
+			remote-port = <0>;
+			enum-name = "I2C_PORT_BATTERY";
+			label = "BATTERY";
+		};
+		virtual {
+			i2c-port = <&i2c0_0>;
+			enum-name = "I2C_PORT_VIRTUAL";
+			label = "VIRTUAL";
+		};
+		charger {
+			i2c-port = <&i2c0_0>;
+			enum-name = "I2C_PORT_CHARGER";
+			label = "CHARGER";
+		};
+		tcpc0 {
+			i2c-port = <&i2c1_0>;
+			enum-name = "I2C_PORT_TCPC0";
+			label = "TCPC0";
+		};
+		tcpc1 {
+			i2c-port = <&i2c2_0>;
+			enum-name = "I2C_PORT_TCPC1";
+			label = "TCPC1";
+		};
+		eeprom {
+			i2c-port = <&i2c5_0>;
+			enum-name = "I2C_PORT_EEPROM";
+			label = "EEPROM";
+		};
+		i2c_sensor: sensor {
+			i2c-port = <&i2c7_0>;
+			enum-name = "I2C_PORT_SENSOR";
+			label = "SENSOR";
+		};
+		accel {
+			i2c-port = <&i2c7_0>;
+			enum-name = "I2C_PORT_ACCEL";
+			label = "ACCEL";
+		};
+	};
+
+	named-pwms {
+		compatible = "named-pwms";
+
+		kblight {
+			pwms = <&pwm3 0 0>;
+			label = "KBLIGHT";
+			frequency = <10000>;
+		};
+		displight {
+			pwms = <&pwm5 0 0>;
+			label = "DISPLIGHT";
+			frequency = <4800>;
+		};
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		vbus {
+			label = "ADC_VBUS";
+			enum-name = "ADC_VBUS";
+			channel = <1>;
+			/* Measure VBUS through a 1/10 voltage divider */
+			mul = <10>;
+		};
+		amon_bmon {
+			label = "ADC_AMON_BMON";
+			enum-name = "ADC_AMON_BMON";
+			channel = <2>;
+			/*
+			 * Adapter current output or battery charging/
+			 * discharging current (uV) 18x amplification on
+			 * charger side.
+			 */
+			mul = <1000>;
+			div = <18>;
+		};
+		psys {
+			label = "ADC_PSYS";
+			enum-name = "ADC_PSYS";
+			channel = <3>;
+			/*
+			 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor,
+			 * to read 0.8V @ 99 W, i.e. 124000 uW/mV.
+			 */
+			mul = <124000>;
+		};
+	};
+
+	def-lvol-io-list {
+		compatible = "nuvoton,npcx-lvolctrl-def";
+
+		/* I2C_SDA0 & SCL0 */
+		lvol-io-pads = <&lvol_iob4 &lvol_iob5>;
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */
+};
+
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+
+	isl9238: isl9238@9 {
+		compatible = "intersil,isl9238";
+		reg = <0x09>;
+		label = "ISL9238_CHARGER";
+	};
+};
+
+&i2c1_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c2_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c3_0 {
+	/* Not used as no WLC connected */
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c5_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c7_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+/* Keyboard backlight */
+&pwm3 {
+	status = "okay";
+};
+
+/* Display backlight */
+&pwm5 {
+	status = "okay";
+};
+
+&adc0 {
+	status = "okay";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&alt7_no_ksi0_sl
+		     &alt7_no_ksi1_sl
+		     &alt7_no_ksi2_sl
+		     &alt7_no_ksi3_sl
+		     &alt7_no_ksi4_sl
+		     &alt7_no_ksi5_sl
+		     &alt7_no_ksi6_sl
+		     &alt7_no_ksi7_sl
+		     &alt8_no_kso00_sl
+		     &alt8_no_kso01_sl
+		     &alt8_no_kso03_sl
+		     &alt8_no_kso04_sl
+		     &alt8_no_kso05_sl
+		     &alt8_no_kso06_sl
+		     &alt8_no_kso07_sl
+		     &alt9_no_kso08_sl
+		     &alt9_no_kso09_sl
+		     &alt9_no_kso10_sl
+		     &alt9_no_kso11_sl
+		     &alt9_no_kso12_sl
+		     >;
+};
diff --git a/zephyr/boards/arm/trogdor/trogdor_defconfig b/zephyr/boards/arm/trogdor/trogdor_defconfig
new file mode 100644
index 0000000000..4011f89a94
--- /dev/null
+++ b/zephyr/boards/arm/trogdor/trogdor_defconfig
@@ -0,0 +1,36 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_NPCX7=y
+CONFIG_SOC_NPCX7M7FC=y
+
+# Platform Configuration
+CONFIG_BOARD_TROGDOR=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinmux Driver
+CONFIG_PINMUX=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# Power Management
+CONFIG_SOC_POWER_MANAGEMENT=y
+CONFIG_PM_POLICY_APP=y
+CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
+CONFIG_SOC_POWER_MANAGEMENT_TRACE=y
diff --git a/zephyr/boards/arm/volteer/Kconfig.board b/zephyr/boards/arm/volteer/Kconfig.board
new file mode 100644
index 0000000000..5a0390e16f
--- /dev/null
+++ b/zephyr/boards/arm/volteer/Kconfig.board
@@ -0,0 +1,13 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Note: this Zephyr board more closely represents the Chrome OS
+# concept of a baseboard.  Zephyr boards and Chrome OS boards do not
+# have a 1:1 mapping.
+config BOARD_VOLTEER
+	bool "Google Volteer Baseboard"
+	depends on SOC_NPCX7M6FC || SOC_NPCX7M7FC
+	# NPCX doesn't actually have enough ram for coverage, but this will
+	# allow generating initial 0 line coverage.
+	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/volteer/Kconfig.defconfig b/zephyr/boards/arm/volteer/Kconfig.defconfig
new file mode 100644
index 0000000000..05361962d9
--- /dev/null
+++ b/zephyr/boards/arm/volteer/Kconfig.defconfig
@@ -0,0 +1,11 @@
+# Google Volteer EC
+
+# Copyright 2020 The Chromium OS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_VOLTEER
+
+config BOARD
+	default "volteer"
+
+endif # BOARD_VOLTEER
diff --git a/zephyr/boards/arm/volteer/board.cmake b/zephyr/boards/arm/volteer/board.cmake
new file mode 100644
index 0000000000..e29e12278d
--- /dev/null
+++ b/zephyr/boards/arm/volteer/board.cmake
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin)
diff --git a/zephyr/boards/arm/volteer/volteer.dts b/zephyr/boards/arm/volteer/volteer.dts
new file mode 100644
index 0000000000..2a1c5c206d
--- /dev/null
+++ b/zephyr/boards/arm/volteer/volteer.dts
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2020 The Chromium OS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <cros/nuvoton/npcx7.dtsi>
+#include <dt-bindings/adc/adc.h>
+#include <dt-bindings/charger/intersil_isl9241.h>
+#include <dt-bindings/gpio_defines.h>
+#include <nuvoton/npcx7m7fc.dtsi>
+
+/ {
+	model = "Google Volteer EC";
+
+	aliases {
+		i2c-0 = &i2c0_0;
+		i2c-1 = &i2c1_0;
+		i2c-2 = &i2c2_0;
+		i2c-3 = &i2c3_0;
+		i2c-5 = &i2c5_0;
+		i2c-7 = &i2c7_0;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,flash = &flash0;
+		cros,rtc = &mtc;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+
+		disabled = "hostcmd";
+	};
+
+	named-batteries {
+		compatible = "named-batteries";
+
+		lgc011 {
+			enum-name = "lgc011";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_sensor: sensor {
+			i2c-port = <&i2c0_0>;
+			enum-name = "I2C_PORT_SENSOR";
+			label = "SENSOR";
+		};
+		i2c-accel {
+			i2c-port = <&i2c0_0>;
+			enum-name = "I2C_PORT_ACCEL";
+			label = "ACCEL";
+		};
+		usb-c0 {
+			i2c-port = <&i2c1_0>;
+			enum-name = "I2C_PORT_USB_C0";
+			label = "USB_C0";
+		};
+		usb-c1 {
+			i2c-port = <&i2c2_0>;
+			enum-name = "I2C_PORT_USB_C1";
+			label = "USB_C1";
+		};
+		usb1-mix {
+			i2c-port = <&i2c3_0>;
+			enum-name = "I2C_PORT_USB_1_MIX";
+			label = "USB_1_MIX";
+		};
+		power {
+			i2c-port = <&i2c5_0>;
+			enum-name = "I2C_PORT_POWER";
+			label = "POWER";
+		};
+		battery {
+			i2c-port = <&i2c5_0>;
+			enum-name = "I2C_PORT_BATTERY";
+			label = "BATTERY";
+		};
+		eeprom {
+			i2c-port = <&i2c7_0>;
+			remote-port = <7>;
+			enum-name = "I2C_PORT_EEPROM";
+			label = "EEPROM";
+		};
+		charger {
+			i2c-port = <&i2c7_0>;
+			enum-name = "I2C_PORT_CHARGER";
+			label = "CHARGER";
+		};
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_charger: charger {
+			label = "ADC_TEMP_SENSOR_CHARGER";
+			enum-name = "ADC_TEMP_SENSOR_CHARGER";
+			channel = <0>;
+		};
+		adc_pp3300_regulator: pp3300_regulator {
+			label = "ADC_TEMP_SENSOR_PP3300_REGULATOR";
+			enum-name = "ADC_TEMP_SENSOR_PP3300_REGULATOR";
+			channel = <1>;
+		};
+		adc_ddr_soc: ddr_soc {
+			label = "ADC_TEMP_SENSOR_DDR_SOC";
+			enum-name = "ADC_TEMP_SENSOR_DDR_SOC";
+			channel = <8>;
+		};
+		adc_fan: fan {
+			label = "ADC_TEMP_SENSOR_FAN";
+			enum-name = "ADC_TEMP_SENSOR_FAN";
+			channel = <3>;
+		};
+	};
+
+	named-temp-sensors {
+		charger {
+			compatible = "temp-3v3-30k9-47k-4050b";
+			label = "TEMP_SENSOR_CHARGER";
+			enum-name = "TEMP_SENSOR_CHARGER";
+			temp_fan_off = <40>;
+			temp_fan_max = <55>;
+			temp_host_high = <75>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <65>;
+			adc = <&adc_charger>;
+		};
+		pp3300_regulator {
+			compatible = "temp-3v3-30k9-47k-4050b";
+			label = "TEMP_SENSOR_PP3300_REGULATOR";
+			enum-name = "TEMP_SENSOR_PP3300_REGULATOR";
+			temp_fan_off = <40>;
+			temp_fan_max = <55>;
+			temp_host_high = <75>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <65>;
+			adc = <&adc_pp3300_regulator>;
+		};
+		ddr_soc {
+			compatible = "temp-3v3-30k9-47k-4050b";
+			label = "TEMP_SENSOR_DDR_SOC";
+			enum-name = "TEMP_SENSOR_DDR_SOC";
+			temp_fan_off = <35>;
+			temp_fan_max = <50>;
+			temp_host_high = <70>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <65>;
+			adc = <&adc_ddr_soc>;
+		};
+		fan {
+			compatible = "temp-3v3-30k9-47k-4050b";
+			label = "TEMP_SENSOR_FAN";
+			enum-name = "TEMP_SENSOR_FAN";
+			temp_fan_off = <35>;
+			temp_fan_max = <50>;
+			temp_host_high = <70>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <65>;
+			adc = <&adc_fan>;
+		};
+	};
+
+	vsby-psl-in-list {
+		/* Use PSL_IN1/2/3/4 as detection pins from hibernate mode */
+		psl-in-pads = <&psl_in1 &psl_in2 &psl_in3 &psl_in4>;
+	};
+
+	/*
+	 * The CBI Second Source Factory Cache (SSFC) layout definition.
+	 * Specific fields values are defined per board.
+	 */
+	cbi-ssfc {
+		compatible = "named-cbi-ssfc";
+
+		cbi_ssfc_base_sensor: base_sensor {
+			enum-name = "BASE_SENSOR";
+			size = <3>;
+		};
+		cbi_ssfc_lid_sensor: lid_sensor {
+			enum-name = "LID_SENSOR";
+			size = <3>;
+		};
+		cbi_ssfc_lightbar: lightbar {
+			enum-name = "LIGHTBAR";
+			size = <2>;
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */
+};
+
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c1_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c2_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c3_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&i2c5_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&i2c7_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	isl9241: isl9241@9 {
+		compatible = "intersil,isl9241";
+		reg = <0x09>;
+		label = "ISL9241_CHARGER";
+		switching-frequency = <SWITCHING_FREQ_724KHZ>;
+	};
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&alt7_no_ksi0_sl
+		     &alt7_no_ksi1_sl
+		     &alt7_no_ksi2_sl
+		     &alt7_no_ksi3_sl
+		     &alt7_no_ksi4_sl
+		     &alt7_no_ksi5_sl
+		     &alt7_no_ksi6_sl
+		     &alt7_no_ksi7_sl
+		     &alt8_no_kso00_sl
+		     &alt8_no_kso01_sl
+		     &alt8_no_kso03_sl
+		     &alt8_no_kso04_sl
+		     &alt8_no_kso05_sl
+		     &alt8_no_kso06_sl
+		     &alt8_no_kso07_sl
+		     &alt9_no_kso08_sl
+		     &alt9_no_kso09_sl
+		     &alt9_no_kso10_sl
+		     &alt9_no_kso11_sl
+		     &alt9_no_kso12_sl
+		     &alt9_no_kso13_sl
+		     &alt9_no_kso14_sl
+		     >;
+};
+
+&adc0 {
+	status = "okay";
+};
+
+/* Power switch logic input pads */
+&psl_in1 {
+	flag = <NPCX_PSL_RISING_EDGE>;
+};
+
+&psl_in2 {
+	flag = <NPCX_PSL_RISING_EDGE>;
+};
+
+&psl_in3 {
+	flag = <NPCX_PSL_FALLING_EDGE>;
+};
+
+&psl_in4 {
+	flag = <NPCX_PSL_RISING_EDGE>;
+};
diff --git a/zephyr/boards/arm/volteer/volteer_defconfig b/zephyr/boards/arm/volteer/volteer_defconfig
new file mode 100644
index 0000000000..d9299c680a
--- /dev/null
+++ b/zephyr/boards/arm/volteer/volteer_defconfig
@@ -0,0 +1,41 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_NPCX7=y
+CONFIG_SOC_NPCX7M7FC=y
+
+# Platform Configuration
+CONFIG_BOARD_VOLTEER=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinmux Driver
+CONFIG_PINMUX=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# ADC
+# The resolution and oversamplig values are fixed by the NPCX ADC driver
+CONFIG_ADC=y
+CONFIG_ADC_SHELL=n
+
+# Power Management
+CONFIG_SOC_POWER_MANAGEMENT=y
+CONFIG_PM_POLICY_APP=y
+CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
+CONFIG_SOC_POWER_MANAGEMENT_TRACE=y