diff options
| author | Jun Lin <CHLin56@nuvoton.com> | 2021-02-22 16:42:05 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-02 03:27:34 +0000 |
| commit | e1aed455f52d28bf419c86431546b476db4e15e5 (patch) | |
| tree | 0e51dfb7e3955a7fdbec6af47663dac1fe140092 /zephyr/drivers/cros_system/cros_system_npcx.c | |
| parent | 2cd7866a7f55aae9453518cb5b06659e7c847c9d (diff) | |
| download | chrome-ec-e1aed455f52d28bf419c86431546b476db4e15e5.tar.gz | |
zephyr: Add initial configuration for debug interface
This CL configures the initial setting for debug interface.
It will also select the device pin to JTAG0 or JTAG1 by adding either
&dbg {
pinctrl-0 = <&alt5_njen0_en>;
status = "okay";
};
or
&dbg {
pinctrl-0 = <&alt5_njen1_en>;
status = "okay";
};
to the board's dts file.
BUG=b:179809145
BRANCH=None.
TEST=observe the registers are set correctly.
Cq-Depend: chromium:2717588, chromium:2717589, chromium:2717590
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I0e3cdeed2974a535bd6d6d0ddaaf291db1d8e1dc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2712142
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Diffstat (limited to 'zephyr/drivers/cros_system/cros_system_npcx.c')
| -rw-r--r-- | zephyr/drivers/cros_system/cros_system_npcx.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/zephyr/drivers/cros_system/cros_system_npcx.c b/zephyr/drivers/cros_system/cros_system_npcx.c index b63743a13d..71eb1c4b9f 100644 --- a/zephyr/drivers/cros_system/cros_system_npcx.c +++ b/zephyr/drivers/cros_system/cros_system_npcx.c @@ -134,3 +134,31 @@ static const struct cros_system_driver_api cros_system_driver_npcx_api = { DEVICE_DEFINE(cros_system_npcx_0, "CROS_SYSTEM", cros_system_npcx_init, NULL, &cros_system_npcx_dev_data, &cros_system_dev_cfg, PRE_KERNEL_1, 30, &cros_system_driver_npcx_api); + +#define HAL_DBG_REG_BASE_ADDR \ + ((struct dbg_reg *)DT_REG_ADDR(DT_INST(0, nuvoton_npcx_cros_dbg))) + +#define DBG_NODE DT_NODELABEL(dbg) +#define DBG_PINCTRL_PH DT_PHANDLE_BY_IDX(DBG_NODE, pinctrl_0, 0) +#define DBG_ALT_FILED(f) DT_PHA_BY_IDX(DBG_PINCTRL_PH, alts, 0, f) + +static int jtag_init(const struct device *dev) +{ + ARG_UNUSED(dev); + struct dbg_reg *const dbg_reg_base = HAL_DBG_REG_BASE_ADDR; + const struct npcx_alt jtag_alts[] = { + { + .group = DBG_ALT_FILED(group), + .bit = DBG_ALT_FILED(bit), + .inverted = DBG_ALT_FILED(inv) + } + }; + + dbg_reg_base->DBGCTRL = 0x04; + dbg_reg_base->DBGFRZEN3 &= ~BIT(NPCX_DBGFRZEN3_GLBL_FRZ_DIS); + if (DT_NODE_HAS_STATUS(DT_NODELABEL(dbg), okay)) + npcx_pinctrl_mux_configure(jtag_alts, 1, 1); + + return 0; +} +SYS_INIT(jtag_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT + 1); |