zephyr: driver: add cros_system driver and chip-reset cause

This CL introduces cros_system driver. Currently, Zephyr doesn't have
the system related API (e.g., reset cause, system reset). Add a
cros_system driver to put those system chip drivers. This CL adds reset
cause function initially.

BUG=b:178101173
BRANCH=None.
TEST=zmake testall
TEST=check reset cause by powerup, reset_pin, debug_rst, watchdog_rst

Cq-Depend: chromium:2661921
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I7c956c2a9c10f3be913400bb33d2f4002dcbabb3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2657912
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Queue: Simon Glass <sjg@chromium.org>

5 files changed, 98 insertions, 0 deletions

diff --git a/zephyr/drivers/CMakeLists.txt b/zephyr/drivers/CMakeLists.txt
index 58998e809a..692eb456a8 100644
--- a/zephyr/drivers/CMakeLists.txt
+++ b/zephyr/drivers/CMakeLists.txt
@@ -5,3 +5,4 @@
 add_subdirectory(cros_bbram)
 add_subdirectory(cros_flash)
 add_subdirectory(cros_kb_raw)
+add_subdirectory(cros_system)
diff --git a/zephyr/drivers/Kconfig b/zephyr/drivers/Kconfig
index 68e9b01229..69f30ce2b2 100644
--- a/zephyr/drivers/Kconfig
+++ b/zephyr/drivers/Kconfig
@@ -5,3 +5,4 @@
 rsource "cros_bbram/Kconfig"
 rsource "cros_flash/Kconfig"
 rsource "cros_kb_raw/Kconfig"
+rsource "cros_system/Kconfig"
diff --git a/zephyr/drivers/cros_system/CMakeLists.txt b/zephyr/drivers/cros_system/CMakeLists.txt
new file mode 100644
index 0000000000..7898442202
--- /dev/null
+++ b/zephyr/drivers/cros_system/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_CROS_SYSTEM_NPCX	cros_system_npcx.c)
diff --git a/zephyr/drivers/cros_system/Kconfig b/zephyr/drivers/cros_system/Kconfig
new file mode 100644
index 0000000000..e1e7163f99
--- /dev/null
+++ b/zephyr/drivers/cros_system/Kconfig
@@ -0,0 +1,13 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig CROS_SYSTEM_NPCX
+	bool "Nuvoton NPCX cros system driver"
+	depends on SOC_FAMILY_NPCX
+	default y
+	help
+	  This option enables the cros system driver for the NPCX family of
+	  processors. Currently, Zephyr doesn't provide the system related API.
+	  The cros system driver provides the low-level driver related to
+	  chromium ec system functionality.
diff --git a/zephyr/drivers/cros_system/cros_system_npcx.c b/zephyr/drivers/cros_system/cros_system_npcx.c
new file mode 100644
index 0000000000..619acaddb5
--- /dev/null
+++ b/zephyr/drivers/cros_system/cros_system_npcx.c
@@ -0,0 +1,78 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <drivers/cros_system.h>
+#include <logging/log.h>
+#include <soc.h>
+
+LOG_MODULE_REGISTER(cros_system, LOG_LEVEL_ERR);
+
+/* Driver config */
+struct cros_system_npcx_config {
+	/* hardware module base address */
+	uintptr_t base_scfg;
+	uintptr_t base_twd;
+};
+
+/* Driver data */
+struct cros_system_npcx_data {
+	int reset; /* reset cause */
+};
+
+/* Driver convenience defines */
+#define DRV_CONFIG(dev) ((const struct cros_system_npcx_config *)(dev)->config)
+
+#define HAL_SCFG_INST(dev) (struct scfg_reg *)(DRV_CONFIG(dev)->base_scfg)
+#define HAL_TWD_INST(dev) (struct twd_reg *)(DRV_CONFIG(dev)->base_twd)
+
+#define DRV_DATA(dev) ((struct cros_system_npcx_data *)(dev)->data)
+
+static int cros_system_npcx_get_reset_cause(const struct device *dev)
+{
+	struct cros_system_npcx_data *data = DRV_DATA(dev);
+
+	return data->reset;
+}
+
+static int cros_system_npcx_init(const struct device *dev)
+{
+	struct scfg_reg *const inst_scfg = HAL_SCFG_INST(dev);
+	struct twd_reg *const inst_twd = HAL_TWD_INST(dev);
+	struct cros_system_npcx_data *data = DRV_DATA(dev);
+
+	/* check reset cause */
+	if (IS_BIT_SET(inst_twd->T0CSR, NPCX_T0CSR_WDRST_STS)) {
+		data->reset = WATCHDOG_RST;
+		inst_twd->T0CSR |= BIT(NPCX_T0CSR_WDRST_STS);
+	} else if (IS_BIT_SET(inst_scfg->RSTCTL, NPCX_RSTCTL_DBGRST_STS)) {
+		data->reset = DEBUG_RST;
+		inst_scfg->RSTCTL |= BIT(NPCX_RSTCTL_DBGRST_STS);
+	} else if (IS_BIT_SET(inst_scfg->RSTCTL, NPCX_RSTCTL_VCC1_RST_STS)) {
+		data->reset = VCC1_RST_PIN;
+	} else {
+		data->reset = POWERUP;
+	}
+
+	return 0;
+}
+
+static struct cros_system_npcx_data cros_system_npcx_dev_data;
+
+static const struct cros_system_npcx_config cros_system_dev_cfg = {
+	.base_scfg = DT_REG_ADDR(DT_INST(0, nuvoton_npcx_pinctrl)),
+	.base_twd = DT_REG_ADDR(DT_INST(0, nuvoton_npcx_watchdog)),
+};
+
+static const struct cros_system_driver_api cros_system_driver_npcx_api = {
+	.get_reset_cause = cros_system_npcx_get_reset_cause,
+};
+
+/*
+ * The priority of cros_system_npcx_init() should be lower than watchdog init
+ * for reset cause check.
+ */
+DEVICE_AND_API_INIT(cros_system_npcx_0, "CROS_SYSTEM", cros_system_npcx_init,
+		    &cros_system_npcx_dev_data, &cros_system_dev_cfg,
+		    PRE_KERNEL_1, 30, &cros_system_driver_npcx_api);