diff options
| author | martin yan <martin.yan@microchip.corp-partner.google.com> | 2021-07-12 08:49:07 -0400 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-07-14 21:00:15 +0000 |
| commit | 58e9704c8f823bebbf2ae426567dd95a8eef6d50 (patch) | |
| tree | 9201cc70becb6edf550c300fb37f3f61c7d348ca /zephyr/dts/bindings/emul/zephyr,bmi.yaml | |
| parent | aa389f6f5b73bdc734d1ff49ae4879419658561b (diff) | |
| download | chrome-ec-58e9704c8f823bebbf2ae426567dd95a8eef6d50.tar.gz | |
mchp: Correct integrated SPI flash pins' configuration
Corrected MEC1727 integrated SPI flash CS# (GPIO116) and CLK (GPIO117)
alternative function as 1 (Internal SPI functionality) from 2 (General
purpose SPI functionality).
BUG=none
BRANCH=none
TEST=Tested on ADL RVP via EC UART console
> sysjump RW: able to switch to RW from RO
> sysjump RO: able to switch to RO from RW
Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: I870925183e670022dc023812265a7ef496b5f255
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3021101
Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'zephyr/dts/bindings/emul/zephyr,bmi.yaml')
0 files changed, 0 insertions, 0 deletions