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author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | 2022-02-25 19:30:45 -0800 |
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committer | Commit Bot <commit-bot@chromium.org> | 2022-03-09 00:58:57 +0000 |
commit | 5e4ae33ebb39a245e31f146925362b772c738548 (patch) | |
tree | 08c4a7437792b61ebf3ae8f2ccc0f0520afe1ad8 /zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml | |
parent | 3fbd8014874439aeb039531b50f62c1fe4a7d032 (diff) | |
download | chrome-ec-5e4ae33ebb39a245e31f146925362b772c738548.tar.gz |
zephyr: subsys/ap_pwrseq: Replace power signal functions
New implementation of X86 power signals offers flexibility to retrieve
signal using different methods without changing interface, this way
we can replace 'intel_x86_get_pg_ec_all_sys_pwrgd' and
'intel_x86_get_pg_ec_dsw_pwrok' with corresponding enum power_signal
using 'power_signal_is_asserted'.
BUG=b:203446068
BRANCH=none
TEST=On Nivviks, AP boots to S0.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I3efacf83dbd02bb3b697538bf3e05d673fabfe17
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3492941
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Commit-Queue: Andrew McRae <amcrae@google.com>
Tested-by: Andrew McRae <amcrae@google.com>
Diffstat (limited to 'zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml')
-rw-r--r-- | zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml b/zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml index 24073dcca4..256320f85b 100644 --- a/zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml +++ b/zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml @@ -22,12 +22,15 @@ properties: Keep in alphebetical order. enum: - PWR_ALL_SYS_PWRGD + - PWR_DSW_PWROK - PWR_EC_PCH_RSMRST - PWR_EC_PCH_SYS_PWROK + - PWR_EC_SOC_DSW_PWROK + - PWR_EN_PP3300_A - PWR_EN_PP5000_A - PWR_IMVP9_VRRDY - PWR_PCH_PWROK - - PWR_DSW_PWROK + - PWR_PG_PP1P05 - PWR_RSMRST - PWR_SLP_S0 - PWR_SLP_S3 |