zephyr: Move bbram logic to devicetree

Move all bbram logic to a common npcx.dtsi file included in
both volteer and kohaku. Updates the bbram access logic in
zephyr/shim/src/system.c to use devicetree. Updates the unit
tests to match.

BRANCH=none
BUG=b:178807203
TEST=zmake testall

Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I2a7c65b92a395c622e8cfe751e4e98b3173e38fb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2669271
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>

1 files changed, 74 insertions, 0 deletions

diff --git a/zephyr/include/cros/nuvoton/npcx.dtsi b/zephyr/include/cros/nuvoton/npcx.dtsi
new file mode 100644
index 0000000000..89fb9484d9
--- /dev/null
+++ b/zephyr/include/cros/nuvoton/npcx.dtsi
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2021 The Chromium OS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+/ {
+
+	named-bbram-regions {
+		compatible = "named-bbram-regions";
+
+		scratchpad {
+			offset = <0x00>;
+			size = <0x04>;
+		};
+		saved-reset-flags {
+			offset = <0x04>;
+			size = <0x04>;
+		};
+		wake {
+			offset = <0x08>;
+			size = <0x04>;
+		};
+		pd0 {
+			offset = <0x0c>;
+			size = <0x01>;
+		};
+		pd1 {
+			offset = <0x0d>;
+			size = <0x01>;
+		};
+		try_slot {
+			offset = <0x0e>;
+			size = <0x01>;
+		};
+		pd2 {
+			offset = <0x0f>;
+			size = <0x01>;
+		};
+		ramlog {
+			offset = <0x20>;
+			size = <0x01>;
+		};
+		panic_flags {
+			offset = <0x23>;
+			size = <0x01>;
+		};
+		panic_bkup {
+			offset = <0x24>;
+			size = <0x1c>;
+		};
+		lct_time {
+			offset = <0x40>;
+			size = <0x04>;
+		};
+	};
+
+	soc {
+
+		bbram: bb-ram@400af000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "nuvoton,npcx-cros-bbram";
+			status = "okay";
+			reg = <0x400af000 0x80
+			       0x400af100 0x1>;
+			reg-names = "memory", "status";
+			label = "BBRAM";
+		};
+	};
+
+};