diff options
| author | Ruibin Chang <Ruibin.Chang@ite.com.tw> | 2021-04-07 15:56:55 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-05-21 02:30:11 +0000 |
| commit | 2488b0595fca9f17cd31d61821512017d3536a0b (patch) | |
| tree | 1103262037301853dc1aef85cf9039b1ee1883c8 /zephyr/include/soc/ite_it8xxx2 | |
| parent | fb99538f460aa1265037bdca0ddaf0222c5860df (diff) | |
| download | chrome-ec-2488b0595fca9f17cd31d61821512017d3536a0b.tar.gz | |
zephyr: add clock to support it8xxx2 cros_kb_row driver
Add clock to support it8xxx2 cros_kb_row driver.
BUG=b:187192587
BRANCH=none
TEST=on hayato, read pll_reg_to_freq is same as setting.
Cq-Depend: chromium:2909732
Change-Id: I9fd9f6ca5c6796ad9aee22a5cf7dc23564d2a814
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2813880
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'zephyr/include/soc/ite_it8xxx2')
| -rw-r--r-- | zephyr/include/soc/ite_it8xxx2/reg_def_cros.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h b/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h index d03d8b41c0..8d3b56878e 100644 --- a/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h +++ b/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h @@ -54,4 +54,44 @@ struct kbs_reg { #define IT8XXX2_KBS_KSO2GCTRL BIT(2) #define IT8XXX2_KBS_KSO2GOEN BIT(2) +/* + * ECPM (EC Clock and Power Management) device registers + */ +struct ecpm_reg { + /* 0x000: Reserved1 */ + volatile uint8_t reserved1; + /* 0x001: Clock Gating Control 1 */ + volatile uint8_t ECPM_CGCTRL1; + /* 0x002: Clock Gating Control 2 */ + volatile uint8_t ECPM_CGCTRL2; + /* 0x003: PLL Control */ + volatile uint8_t ECPM_PLLCTRL; + /* 0x004: Auto Clock Gating */ + volatile uint8_t ECPM_AUTOCG; + /* 0x005: Clock Gating Control 3 */ + volatile uint8_t ECPM_CGCTRL3; + /* 0x006: PLL Frequency */ + volatile uint8_t ECPM_PLLFREQ; + /* 0x007: Reserved2 */ + volatile uint8_t reserved2; + /* 0x008: PLL Clock Source Status */ + volatile uint8_t ECPM_PLLCSS; + /* 0x009: Clock Gating Control 4 */ + volatile uint8_t ECPM_CGCTRL4; + /* 0x00A: Reserved3 */ + volatile uint8_t reserved3; + /* 0x00B: Reserved4 */ + volatile uint8_t reserved4; + /* 0x00C: System Clock Divide Control 0 */ + volatile uint8_t ECPM_SCDCR0; + /* 0x00D: System Clock Divide Control 1 */ + volatile uint8_t ECPM_SCDCR1; + /* 0x00E: System Clock Divide Control 2 */ + volatile uint8_t ECPM_SCDCR2; + /* 0x00F: System Clock Divide Control 3 */ + volatile uint8_t ECPM_SCDCR3; + /* 0x010: System Clock Divide Control 4 */ + volatile uint8_t ECPM_SCDCR4; +}; + #endif /* _ITE_IT8XXX2_REG_DEF_CROS_H */ |