Merge remote-tracking branch cros/main into firmware-nissa-15217.B-mainfirmware-nissa-15217.126.B-main

Generated by: ./util/update_release_branch.py --zephyr --board nissa firmware-
nissa-15217.B-main

Relevant changes:

git log --oneline dce247e979..0849542c72 -- zephyr/program/nissa
util/getversion.sh

0849542c72 zephyr: add sleep property for keyboard factory test
5825d894b9 nissa: disable PLATFORM_EC_TCPC_INTERRUPT
25a400690f yavikso: Update fan table version 3
9263f14536 zephyr: remove shi node and add references to shi0
b40c6970d3 Craask: Charger limit for 65w adapter
6fd2d3ea6c zephyr: add comments for tcpc driver
00986ffb1c zephyr: move usbc interrupt handler to shim
2508094b14 yaviks: reduce RW image size (64KB)
55b6aaf52f yaviks: enable keyboard factory test
4786d1eac6 nissa: Add ocpc init function to Nissa boards
2ae1083638 zephyr: cros_kb: set KSI/KSO kbs mode by pinctrl driver
d415f4665a yaviks: Fix OCPC Vsys overshooting
93f9d42a7c zephyr: config: drop few more redundant options

BRANCH=None
BUG=b:254148652 b:260762509 b:265220075 b:268273712 b:265763662
BUG=b:253557900 b:254148652 b:269212593 b:267404783 b:262352202
TEST=`make -j buildall`

Force-Relevant-Builds: all
Change-Id: I195dd82af114180b611f9afd1465a69f7f43d417
Signed-off-by: Peter Marheine <pmarheine@chromium.org>

1 files changed, 0 insertions, 83 deletions

diff --git a/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h b/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h
index ef3051e3de..16012c083e 100644
--- a/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h
+++ b/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h
@@ -25,87 +25,4 @@ struct mtc_reg {
 #define NPCX_WTC_PTO 30
 #define NPCX_WTC_WIE 31
 
-/* SHI (Serial Host Interface) registers */
-struct cros_shi_reg {
-	volatile uint8_t reserved1;
-	/* 0x001: SHI Configuration 1 */
-	volatile uint8_t SHICFG1;
-	/* 0x002: SHI Configuration 2 */
-	volatile uint8_t SHICFG2;
-	volatile uint8_t reserved2[2];
-	/* 0x005: Event Enable */
-	volatile uint8_t EVENABLE;
-	/* 0x006: Event Status */
-	volatile uint8_t EVSTAT;
-	/* 0x007: SHI Capabilities */
-	volatile uint8_t CAPABILITY;
-	/* 0x008: Status */
-	volatile uint8_t STATUS;
-	volatile uint8_t reserved3;
-	/* 0x00A: Input Buffer Status */
-	volatile uint8_t IBUFSTAT;
-	/* 0x00B: Output Buffer Status */
-	volatile uint8_t OBUFSTAT;
-	/* 0x00C: SHI Configuration 3 */
-	volatile uint8_t SHICFG3;
-	/* 0x00D: SHI Configuration 4 */
-	volatile uint8_t SHICFG4;
-	/* 0x00E: SHI Configuration 5 */
-	volatile uint8_t SHICFG5;
-	/* 0x00F: Event Status 2 */
-	volatile uint8_t EVSTAT2;
-	/* 0x010: Event Enable 2 */
-	volatile uint8_t EVENABLE2;
-	volatile uint8_t reserved4[15];
-	/* 0x20~0x9F: Output Buffer */
-	volatile uint8_t OBUF[128];
-	/* 0xA0~0x11F: Input Buffer */
-	volatile uint8_t IBUF[128];
-};
-
-/* SHI register fields */
-#define NPCX_SHICFG1_EN 0
-#define NPCX_SHICFG1_MODE 1
-#define NPCX_SHICFG1_WEN 2
-#define NPCX_SHICFG1_AUTIBF 3
-#define NPCX_SHICFG1_AUTOBE 4
-#define NPCX_SHICFG1_DAS 5
-#define NPCX_SHICFG1_CPOL 6
-#define NPCX_SHICFG1_IWRAP 7
-#define NPCX_SHICFG2_SIMUL 0
-#define NPCX_SHICFG2_BUSY 1
-#define NPCX_SHICFG2_ONESHOT 2
-#define NPCX_SHICFG2_SLWU 3
-#define NPCX_SHICFG2_REEN 4
-#define NPCX_SHICFG2_RESTART 5
-#define NPCX_SHICFG2_REEVEN 6
-#define NPCX_EVENABLE_OBEEN 0
-#define NPCX_EVENABLE_OBHEEN 1
-#define NPCX_EVENABLE_IBFEN 2
-#define NPCX_EVENABLE_IBHFEN 3
-#define NPCX_EVENABLE_EOREN 4
-#define NPCX_EVENABLE_EOWEN 5
-#define NPCX_EVENABLE_STSREN 6
-#define NPCX_EVENABLE_IBOREN 7
-#define NPCX_EVSTAT_OBE 0
-#define NPCX_EVSTAT_OBHE 1
-#define NPCX_EVSTAT_IBF 2
-#define NPCX_EVSTAT_IBHF 3
-#define NPCX_EVSTAT_EOR 4
-#define NPCX_EVSTAT_EOW 5
-#define NPCX_EVSTAT_STSR 6
-#define NPCX_EVSTAT_IBOR 7
-#define NPCX_STATUS_OBES 6
-#define NPCX_STATUS_IBFS 7
-#define NPCX_SHICFG3_OBUFLVLDIS 7
-#define NPCX_SHICFG4_IBUFLVLDIS 7
-#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6)
-#define NPCX_SHICFG5_IBUFLVL2DIS 7
-#define NPCX_EVSTAT2_IBHF2 0
-#define NPCX_EVSTAT2_CSNRE 1
-#define NPCX_EVSTAT2_CSNFE 2
-#define NPCX_EVENABLE2_IBHF2EN 0
-#define NPCX_EVENABLE2_CSNREEN 1
-#define NPCX_EVENABLE2_CSNFEEN 2
-
 #endif /* _NUVOTON_NPCX_REG_DEF_CROS_H */