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| author | Jun Lin <CHLin56@nuvoton.com> | 2021-03-26 17:29:16 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-31 15:22:58 +0000 |
| commit | 6f75875da06461dd65f13e2741e16034d27b0289 (patch) | |
| tree | b01d31e859c9c04ee828b08e8d98262c9952351b /zephyr/include/soc | |
| parent | cf62c88b539f0ebc8935a8cf9c375002e7a9e33f (diff) | |
| download | chrome-ec-6f75875da06461dd65f13e2741e16034d27b0289.tar.gz | |
zephyr: npcx: support SHI driver
Add the support for SHI (Serial Host Interface) driver. This is used to
transfer host commands between EC and ARM-based AP.
BUG=b:182600858
BRANCH=none
TEST=Test host command "version" and "Hello" on npcx7_evb and the host
emulator.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I5f290fe910600162764f5728f094dd0f42d508ef
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2786887
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Jack Rosenthal <jrosenth@chromium.org>
Diffstat (limited to 'zephyr/include/soc')
| -rw-r--r-- | zephyr/include/soc/nuvoton_npcx/reg_def_cros.h | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h b/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h index 7b577bed32..8702502a13 100644 --- a/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h +++ b/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h @@ -165,4 +165,87 @@ struct mtc_reg { #define NPCX_WTC_PTO 30 #define NPCX_WTC_WIE 31 +/* SHI (Serial Host Interface) registers */ +struct shi_reg { + volatile uint8_t reserved1; + /* 0x001: SHI Configuration 1 */ + volatile uint8_t SHICFG1; + /* 0x002: SHI Configuration 2 */ + volatile uint8_t SHICFG2; + volatile uint8_t reserved2[2]; + /* 0x005: Event Enable */ + volatile uint8_t EVENABLE; + /* 0x006: Event Status */ + volatile uint8_t EVSTAT; + /* 0x007: SHI Capabilities */ + volatile uint8_t CAPABILITY; + /* 0x008: Status */ + volatile uint8_t STATUS; + volatile uint8_t reserved3; + /* 0x00A: Input Buffer Status */ + volatile uint8_t IBUFSTAT; + /* 0x00B: Output Buffer Status */ + volatile uint8_t OBUFSTAT; + /* 0x00C: SHI Configuration 3 */ + volatile uint8_t SHICFG3; + /* 0x00D: SHI Configuration 4 */ + volatile uint8_t SHICFG4; + /* 0x00E: SHI Configuration 5 */ + volatile uint8_t SHICFG5; + /* 0x00F: Event Status 2 */ + volatile uint8_t EVSTAT2; + /* 0x010: Event Enable 2 */ + volatile uint8_t EVENABLE2; + volatile uint8_t reserved4[15]; + /* 0x20~0x9F: Output Buffer */ + volatile uint8_t OBUF[128]; + /* 0xA0~0x11F: Input Buffer */ + volatile uint8_t IBUF[128]; +}; + +/* SHI register fields */ +#define NPCX_SHICFG1_EN 0 +#define NPCX_SHICFG1_MODE 1 +#define NPCX_SHICFG1_WEN 2 +#define NPCX_SHICFG1_AUTIBF 3 +#define NPCX_SHICFG1_AUTOBE 4 +#define NPCX_SHICFG1_DAS 5 +#define NPCX_SHICFG1_CPOL 6 +#define NPCX_SHICFG1_IWRAP 7 +#define NPCX_SHICFG2_SIMUL 0 +#define NPCX_SHICFG2_BUSY 1 +#define NPCX_SHICFG2_ONESHOT 2 +#define NPCX_SHICFG2_SLWU 3 +#define NPCX_SHICFG2_REEN 4 +#define NPCX_SHICFG2_RESTART 5 +#define NPCX_SHICFG2_REEVEN 6 +#define NPCX_EVENABLE_OBEEN 0 +#define NPCX_EVENABLE_OBHEEN 1 +#define NPCX_EVENABLE_IBFEN 2 +#define NPCX_EVENABLE_IBHFEN 3 +#define NPCX_EVENABLE_EOREN 4 +#define NPCX_EVENABLE_EOWEN 5 +#define NPCX_EVENABLE_STSREN 6 +#define NPCX_EVENABLE_IBOREN 7 +#define NPCX_EVSTAT_OBE 0 +#define NPCX_EVSTAT_OBHE 1 +#define NPCX_EVSTAT_IBF 2 +#define NPCX_EVSTAT_IBHF 3 +#define NPCX_EVSTAT_EOR 4 +#define NPCX_EVSTAT_EOW 5 +#define NPCX_EVSTAT_STSR 6 +#define NPCX_EVSTAT_IBOR 7 +#define NPCX_STATUS_OBES 6 +#define NPCX_STATUS_IBFS 7 +#define NPCX_SHICFG3_OBUFLVLDIS 7 +#define NPCX_SHICFG4_IBUFLVLDIS 7 +#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6) +#define NPCX_SHICFG5_IBUFLVL2DIS 7 +#define NPCX_EVSTAT2_IBHF2 0 +#define NPCX_EVSTAT2_CSNRE 1 +#define NPCX_EVSTAT2_CSNFE 2 +#define NPCX_EVENABLE2_IBHF2EN 0 +#define NPCX_EVENABLE2_CSNREEN 1 +#define NPCX_EVENABLE2_CSNFEEN 2 + #endif /* _NUVOTON_NPCX_REG_DEF_CROS_H */ |