diff options
author | YH Lin <yueherngl@google.com> | 2022-11-30 21:44:08 +0000 |
---|---|---|
committer | YH Lin <yueherngl@google.com> | 2022-11-30 21:44:08 +0000 |
commit | af25602b15b22b9ef5821dcba9934311f2157c48 (patch) | |
tree | d0c89ae8814c2ba35c238c6c0644ec6b1602c63a /zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts | |
parent | 54462f034b635260dd09173b3d082e47fc960ef3 (diff) | |
parent | aa40b859b3a73e5a205bc561c1a29eff38485461 (diff) | |
download | chrome-ec-af25602b15b22b9ef5821dcba9934311f2157c48.tar.gz |
Merge remote-tracking branch cros/main into factory-brya-14517.B-main
Generated by: util/update_release_branch.py --baseboard brya --relevant_paths_file
baseboard/brya/relevant-paths.txt factory-brya-14517.B-main
Relevant changes:
git log --oneline 54462f034b..aa40b859b3 -- baseboard/brya board/agah
board/anahera board/banshee board/brya board/crota board/felwinter
board/gimble board/kano board/mithrax board/osiris board/primus
board/redrix board/taeko board/taniks board/vell board/volmar
driver/bc12/pi3usb9201_public.* driver/charger/bq25710.*
driver/ppc/nx20p348x.* driver/ppc/syv682x_public.*
driver/retimer/bb_retimer_public.* driver/tcpm/nct38xx.*
driver/tcpm/ps8xxx_public.* driver/tcpm/tcpci.* include/power/alderlake*
include/intel_x86.h power/alderlake* power/intel_x86.c
util/getversion.sh
e6da633c38 driver: Sort header files
234a87ae2d tcpci: Add FRS enable to driver structure
a56be59ccd tcpm_header: add test for tcpm_dump_registers
57b3256963 Rename CONFIG_CHARGER_INPUT_CURRENT to _CHARGER_DEFAULT_CURRENT_LIMIT
e420c8ff9a marasov: Modify TypeC and TypeA configuration.
43b53e0045 Add default implementation of board_set_charge_limit
b75dc90677 Add CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT
f1b563c350 baseboard: Sort header files
7d01b1e58d driver/retimer/ps8818.h: Add I2C ADDR FLAGS 0x30, 0x58, 0x70
ec31407993 Add CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
8f89f69a5b crota: disable lid angle sensor for clamshell
BRANCH=None
BUG=b:259002141 b:255184961 b:247100970 b:259354679 b:260630630
BUG=b:163093572 b:254328661
TEST=`emerge-brya chromeos-ec`
Force-Relevant-Builds: all
Change-Id: Ia85a701fbf6b8e67ec214b9e25e0e55e980a6f47
Signed-off-by: YH Lin <yueherngl@google.com>
Diffstat (limited to 'zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts')
-rw-r--r-- | zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts | 125 |
1 files changed, 125 insertions, 0 deletions
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts new file mode 100644 index 0000000000..3c270d296f --- /dev/null +++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts @@ -0,0 +1,125 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <3>; + all-sys-pwrgd-timeout = <20>; + sys-reset-delay = <60>; + }; + + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpioc 4 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio6 6 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 4 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpioa 1 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpiod 3 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpiof 5 GPIO_OPEN_DRAIN>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s3 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S3 virtual wire input from PCH"; + enum-name = "PWR_SLP_S3"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S3"; + vw-invert; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + gpios = <&gpio7 0 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&en_pp3300_a { + no-auto-init; +}; +&rsmrst_pwrgd { + no-auto-init; +}; +&ec_pch_rsmrst_l { + no-auto-init; +}; +&pch_slp_s0_n { + no-auto-init; +}; +&ec_pch_pwrok_od { + no-auto-init; +}; +&sys_pwrok_ec { + no-auto-init; +}; +&sys_rst_odl { + no-auto-init; +}; +&all_sys_pwrgd { + no-auto-init; +}; |