Revert "Merge remote-tracking branch cros/main into factory-brya-14909.124.B-main"factory-brya-14909.124.B-main

This reverts commit 184d13e77614be3be5374d3fef9d1edf66ec8687.

Reason for revert: broken build due to ec-utils.

Original change's description:
> Merge remote-tracking branch cros/main into factory-brya-14909.124.B-main
>
> Generated by: util/update_release_branch.py --baseboard brya --relevant_paths_file
> baseboard/brya/relevant-paths.txt factory-brya-14909.124.B-main
>
> Relevant changes:
>
> git log --oneline 19d4d68ffa..aa40b859b3 -- baseboard/brya board/agah
> board/anahera board/banshee board/brya board/crota board/felwinter
> board/gimble board/kano board/mithrax board/osiris board/primus
> board/redrix board/taeko board/taniks board/vell board/volmar
> driver/bc12/pi3usb9201_public.* driver/charger/bq25710.*
> driver/ppc/nx20p348x.* driver/ppc/syv682x_public.*
> driver/retimer/bb_retimer_public.* driver/tcpm/nct38xx.*
> driver/tcpm/ps8xxx_public.* driver/tcpm/tcpci.* include/power/alderlake*
> include/intel_x86.h power/alderlake* power/intel_x86.c
> util/getversion.sh
>
> e6da633c38 driver: Sort header files
> 234a87ae2d tcpci: Add FRS enable to driver structure
> a56be59ccd tcpm_header: add test for tcpm_dump_registers
> 57b3256963 Rename CONFIG_CHARGER_INPUT_CURRENT to _CHARGER_DEFAULT_CURRENT_LIMIT
> e420c8ff9a marasov: Modify TypeC and TypeA configuration.
> 43b53e0045 Add default implementation of board_set_charge_limit
> b75dc90677 Add CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT
> f1b563c350 baseboard: Sort header files
> 7d01b1e58d driver/retimer/ps8818.h: Add I2C ADDR FLAGS 0x30, 0x58, 0x70
> ec31407993 Add CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
> 8f89f69a5b crota: disable lid angle sensor for clamshell
>
> BRANCH=None
> BUG=b:260630630 b:163093572 b:259002141 b:255184961 b:259354679
> BUG=b:247100970 b:254328661
> TEST=`emerge-brya chromeos-ec`
>
> Force-Relevant-Builds: all
> Change-Id: I0ecfa0e6af68631283c7a9e8f1afb9d827176c62
> Signed-off-by: YH Lin <yueherngl@google.com>

Bug: b:260630630 b:163093572 b:259002141 b:255184961 b:259354679
Bug: b:247100970 b:254328661
Change-Id: Ia14942d1bd6a502062399d77cb59d1f4b549b2c9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4077247
Auto-Submit: YH Lin <yueherngl@chromium.org>
Tested-by: YH Lin <yueherngl@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Commit-Queue: YH Lin <yueherngl@chromium.org>

1 files changed, 0 insertions, 152 deletions

diff --git a/zephyr/program/rex/power_signals.dts b/zephyr/program/rex/power_signals.dts
deleted file mode 100644
index 09c84b8558..0000000000
--- a/zephyr/program/rex/power_signals.dts
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Copyright 2022 The ChromiumOS Authors
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	chosen {
-		intel-ap-pwrseq,espi = &espi0;
-	};
-
-	common-pwrseq {
-		compatible = "intel,ap-pwrseq";
-
-		sys-pwrok-delay = <3>;
-		all-sys-pwrgd-timeout = <20>;
-	};
-
-	pwr-en-pp3300-s5 {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "PP1800_S5/PP3300_S5 enable output to LS";
-		enum-name = "PWR_EN_PP3300_A";
-		gpios = <&gpiob 6 GPIO_ACTIVE_HIGH>;
-		output;
-	};
-	pwr-pg-ec-rsmrst-od {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "RSMRST power good from regulator";
-		enum-name = "PWR_RSMRST";
-		gpios = <&gpioe 2 GPIO_ACTIVE_HIGH>;
-		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
-	};
-	pwr-ec-pch-rsmrst-odl {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "RSMRST output to PCH";
-		enum-name = "PWR_EC_PCH_RSMRST";
-		gpios = <&gpioa 6 GPIO_ACTIVE_HIGH>;
-		output;
-	};
-	pwr-pch-pwrok {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "PCH_PWROK output to PCH";
-		enum-name = "PWR_PCH_PWROK";
-		gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
-		output;
-	};
-	pwr-ec-pch-sys-pwrok {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "SYS_PWROK output to PCH";
-		enum-name = "PWR_EC_PCH_SYS_PWROK";
-		gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
-		output;
-	};
-	pwr-sys-rst-l {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "SYS_RESET# output to PCH";
-		enum-name = "PWR_SYS_RST";
-		gpios = <&gpioc 5 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
-		output;
-	};
-	pwr-slp-s0-l {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "SLP_S0_L input from PCH";
-		enum-name = "PWR_SLP_S0";
-		gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
-		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
-	};
-	pwr-slp-s3-l {
-		compatible = "intel,ap-pwrseq-vw";
-		dbg-label = "SLP_S3_L input from PCH";
-		enum-name = "PWR_SLP_S3";
-		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
-		vw-invert;
-/*
- * TODO: Initially, use virtual wire for sleep S3 signal instead of
- * of the GPIO signal which also exists.
- *		compatible = "intel,ap-pwrseq-gpio";
- *		gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
- *		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
- */
-	};
-	pwr-slp-s4 {
-		compatible = "intel,ap-pwrseq-vw";
-		dbg-label = "SLP_S4 virtual wire input from PCH";
-		enum-name = "PWR_SLP_S4";
-		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
-		vw-invert;
-	};
-	pwr-slp-s5 {
-		compatible = "intel,ap-pwrseq-vw";
-		dbg-label = "SLP_S5 virtual wire input from PCH";
-		enum-name = "PWR_SLP_S5";
-		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
-		vw-invert;
-	};
-	pwr-all-sys-pwrgd {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "all power good";
-		enum-name = "PWR_ALL_SYS_PWRGD";
-		gpios = <&gpiof 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
-		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
-	};
-};
-
-/*
- * Because the power signals directly reference the GPIOs,
- * the corresponding named-gpios need to have no-auto-init set.
- */
- /* pwr-en-pp3300-s5 */
-&gpio_en_s5_rails {
-	no-auto-init;
-};
-
-/* pwr-pg-ec-rsmrst-od */
-&gpio_seq_ec_rsmrst_odl {
-	no-auto-init;
-};
-
-/* pwr-ec-pch-rsmrst-odl */
-&gpio_ec_soc_rsmrst_l {
-	no-auto-init;
-};
-
-/* pwr-pch-pwrok */
-&gpio_soc_pwrok {
-	no-auto-init;
-};
-
-/* pwr-ec-pch-sys-pwrok */
-&gpio_sys_pwrok {
-	no-auto-init;
-};
-
-/* pwr-sys-rst-l */
-&gpio_sys_rst_odl {
-	no-auto-init;
-};
-
-/* pwr-slp-s0-l */
-&gpio_sys_slp_s0ix_3v3_l {
-	no-auto-init;
-};
-
-/* pwr-slp-s3-l */
-&gpio_slp_s3_ls_l {
-	no-auto-init;
-};
-
-/* pwr-all-sys-pwrgd */
-&gpio_seq_ec_all_sys_pg {
-	no-auto-init;
-};
-