diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2021-09-17 16:02:42 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-09-17 23:51:26 +0000 |
| commit | ef1a31ced60aba0e1b54c8ae2c28e6c3fdd6f4c1 (patch) | |
| tree | 51e9026515fcffd4c9fee4030df2f90c078ff180 /zephyr/projects/guybrush/gpio.dts | |
| parent | bcf687bce6f31a10e60e831c3f5133a3e5332401 (diff) | |
| download | chrome-ec-ef1a31ced60aba0e1b54c8ae2c28e6c3fdd6f4c1.tar.gz | |
zephyr: guybrush: Bringup power sequencing
Bringup power sequencing for AMD and enable for guybrush.
Note that at the moment we had to copy-paste the power signals and
related funcitons, the code was a bit too far from shimming without
extensive editing. We can try and merge together later.
BUG=b:195137794
BRANCH=none
TEST=power sequence to S0, nothing useful on ap console (yet!)
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I9a577e24d80fe0ff992af4b847e14695b82f871d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3169568
Reviewed-by: Diana Z <dzigterman@chromium.org>
Diffstat (limited to 'zephyr/projects/guybrush/gpio.dts')
| -rw-r--r-- | zephyr/projects/guybrush/gpio.dts | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/zephyr/projects/guybrush/gpio.dts b/zephyr/projects/guybrush/gpio.dts index 60f8be941e..430d4c3755 100644 --- a/zephyr/projects/guybrush/gpio.dts +++ b/zephyr/projects/guybrush/gpio.dts @@ -23,26 +23,32 @@ ec_pwr_btn_odl { gpios = <&gpio0 1 GPIO_INPUT>; label = "EC_PWR_BTN_ODL"; + enum-name = "GPIO_EC_PWR_BTN_ODL"; }; slp_s3_l { gpios = <&gpio6 1 GPIO_INPUT>; label = "SLP_S3_L"; + enum-name = "GPIO_PCH_SLP_S3_L"; }; slp_s5_l { gpios = <&gpio7 2 GPIO_INPUT>; label = "SLP_S5_L"; + enum-name = "GPIO_PCH_SLP_S5_L"; }; slp_s3_s0i3_l { gpios = <&gpio7 4 GPIO_INPUT>; label = "SLP_S3_S0I3_L"; + enum-name = "GPIO_PCH_SLP_S0_L"; }; pg_pwr_s5 { gpios = <&gpioc 0 GPIO_INPUT>; label = "PG_PWR_S5"; + enum-name = "GPIO_S5_PGOOD"; }; pg_pcore_s0_r_od { gpios = <&gpiob 6 GPIO_INPUT>; label = "PG_PCORE_S0_R_OD"; + enum-name = "GPIO_S0_PGOOD"; }; acok_od { gpios = <&gpio0 0 GPIO_INPUT>; @@ -52,26 +58,32 @@ ec_pcore_int_odl { gpios = <&gpiof 0 (GPIO_INPUT | GPIO_PULL_UP)>; label = "EC_PCORE_INT_ODL"; + enum-name = "GPIO_EC_PCORE_INT_ODL"; }; pg_groupc_s0_od { gpios = <&gpioa 3 GPIO_INPUT>; label = "PG_GROUPC_S0_OD"; + enum-name = "GPIO_PG_GROUPC_S0_OD"; }; pg_lpddr4x_s3_od { gpios = <&gpio9 5 GPIO_INPUT>; label = "PG_LPDDR4X_S3_OD"; + enum-name = "GPIO_PG_LPDDR4X_S3_OD"; }; en_pwr_s5 { gpios = <&gpiob 7 GPIO_OUT_LOW>; label = "EN_PWR_S5"; + enum-name = "GPIO_EN_PWR_A"; }; en_pwr_s0_r { gpios = <&gpiof 1 GPIO_OUT_LOW>; label = "EN_PWR_S0_R"; + enum-name = "GPIO_EN_PWR_S0_R"; }; en_pwr_pcore_s0_r { gpios = <&gpioe 1 GPIO_OUT_LOW>; label = "EN_PWR_PCORE_S0_R"; + enum-name = "GPIO_EN_PWR_PCORE_S0_R"; }; ec_entering_rw { gpios = <&gpio6 6 GPIO_OUT_LOW>; @@ -81,10 +93,12 @@ ec_sys_rst_l { gpios = <&gpio7 6 GPIO_ODR_HIGH>; label = "EC_SYS_RST_L"; + enum-name = "GPIO_SYS_RESET_L"; }; ec_soc_rsmrst_l { gpios = <&gpioc 5 GPIO_OUT_LOW>; label = "EC_SOC_RSMRST_L"; + enum-name = "GPIO_PCH_RSMRST_L"; }; ec_clr_cmos { gpios = <&gpioa 1 GPIO_OUT_LOW>; @@ -97,10 +111,12 @@ ec_soc_pwr_btn_l { gpios = <&gpio6 3 GPIO_OUT_HIGH>; label = "EC_SOC_PWR_BTN_L"; + enum-name = "GPIO_PCH_PWRBTN_L"; }; ec_soc_pwr_good { gpios = <&gpiod 3 GPIO_OUT_LOW>; label = "EC_SOC_PWR_GOOD"; + enum-name = "GPIO_PCH_SYS_PWROK"; }; ec_soc_wake_l { gpios = <&gpio0 3 GPIO_OUT_HIGH>; @@ -114,6 +130,7 @@ prochot_odl { gpios = <&gpiod 5 GPIO_ODR_HIGH>; label = "PROCHOT_ODL"; + enum-name = "GPIO_CPU_PROCHOT"; }; soc_alert_ec_l { gpios = <&gpioe 2 GPIO_INPUT>; |