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author | YH Lin <yueherngl@chromium.org> | 2022-12-03 00:17:55 +0000 |
---|---|---|
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-12-05 17:43:18 +0000 |
commit | dd732876495ed4942d00b9f9ca8dd3b01bad7120 (patch) | |
tree | bdff671e5ad3e71e30ab56f4f084f34a2fd72e28 /zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h | |
parent | 184d13e77614be3be5374d3fef9d1edf66ec8687 (diff) | |
download | chrome-ec-dd732876495ed4942d00b9f9ca8dd3b01bad7120.tar.gz |
Revert "Merge remote-tracking branch cros/main into factory-brya-14909.124.B-main"factory-brya-14909.124.B-main
This reverts commit 184d13e77614be3be5374d3fef9d1edf66ec8687.
Reason for revert: broken build due to ec-utils.
Original change's description:
> Merge remote-tracking branch cros/main into factory-brya-14909.124.B-main
>
> Generated by: util/update_release_branch.py --baseboard brya --relevant_paths_file
> baseboard/brya/relevant-paths.txt factory-brya-14909.124.B-main
>
> Relevant changes:
>
> git log --oneline 19d4d68ffa..aa40b859b3 -- baseboard/brya board/agah
> board/anahera board/banshee board/brya board/crota board/felwinter
> board/gimble board/kano board/mithrax board/osiris board/primus
> board/redrix board/taeko board/taniks board/vell board/volmar
> driver/bc12/pi3usb9201_public.* driver/charger/bq25710.*
> driver/ppc/nx20p348x.* driver/ppc/syv682x_public.*
> driver/retimer/bb_retimer_public.* driver/tcpm/nct38xx.*
> driver/tcpm/ps8xxx_public.* driver/tcpm/tcpci.* include/power/alderlake*
> include/intel_x86.h power/alderlake* power/intel_x86.c
> util/getversion.sh
>
> e6da633c38 driver: Sort header files
> 234a87ae2d tcpci: Add FRS enable to driver structure
> a56be59ccd tcpm_header: add test for tcpm_dump_registers
> 57b3256963 Rename CONFIG_CHARGER_INPUT_CURRENT to _CHARGER_DEFAULT_CURRENT_LIMIT
> e420c8ff9a marasov: Modify TypeC and TypeA configuration.
> 43b53e0045 Add default implementation of board_set_charge_limit
> b75dc90677 Add CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT
> f1b563c350 baseboard: Sort header files
> 7d01b1e58d driver/retimer/ps8818.h: Add I2C ADDR FLAGS 0x30, 0x58, 0x70
> ec31407993 Add CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
> 8f89f69a5b crota: disable lid angle sensor for clamshell
>
> BRANCH=None
> BUG=b:260630630 b:163093572 b:259002141 b:255184961 b:259354679
> BUG=b:247100970 b:254328661
> TEST=`emerge-brya chromeos-ec`
>
> Force-Relevant-Builds: all
> Change-Id: I0ecfa0e6af68631283c7a9e8f1afb9d827176c62
> Signed-off-by: YH Lin <yueherngl@google.com>
Bug: b:260630630 b:163093572 b:259002141 b:255184961 b:259354679
Bug: b:247100970 b:254328661
Change-Id: Ia14942d1bd6a502062399d77cb59d1f4b549b2c9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4077247
Auto-Submit: YH Lin <yueherngl@chromium.org>
Tested-by: YH Lin <yueherngl@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Commit-Queue: YH Lin <yueherngl@chromium.org>
Diffstat (limited to 'zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h')
-rw-r--r-- | zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h new file mode 100644 index 0000000000..135fd4ef4f --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h @@ -0,0 +1,58 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel ADL-RVP specific configuration */ + +#ifndef __ADLRVP_BOARD_H +#define __ADLRVP_BOARD_H + +#include "config.h" + +#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 +#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 + +#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 + +/* SOC side BB retimers (dual retimer config) */ +#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 +#if defined(HAS_TASK_PD_C1) +#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 +#endif + +#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 +#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 +#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 +#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 +#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 +#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 +#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 +#define ADL_RVP_BOARD_ID(id) ((id)&0x3F) + +#define CONFIG_BATTERY_TYPE_NO_AUTO_DETECT + +enum adlrvp_charge_ports { + TYPE_C_PORT_0, +#if defined(HAS_TASK_PD_C1) + TYPE_C_PORT_1, +#endif +#if defined(HAS_TASK_PD_C2) + TYPE_C_PORT_2, +#endif +#if defined(HAS_TASK_PD_C3) + TYPE_C_PORT_3, +#endif +}; + +enum ioex_port { + IOEX_C0_PCA9675, + IOEX_C1_PCA9675, +#if defined(HAS_TASK_PD_C2) + IOEX_C2_PCA9675, + IOEX_C3_PCA9675, +#endif + IOEX_PORT_COUNT +}; + +#endif /* __ADLRVP_BOARD_H */ |