diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2021-01-15 11:47:26 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-01-22 17:52:00 +0000 |
| commit | d5ac31e514931ffe64f52694ac4acc86973f9c3b (patch) | |
| tree | 4480e4275e931ccdcc0e911f4e655c8f1cf232d6 /zephyr/projects/kohaku/include/gpio_map.h | |
| parent | 4fb279799bd7c3f92fdf298d33c35f7a29ad0550 (diff) | |
| download | chrome-ec-d5ac31e514931ffe64f52694ac4acc86973f9c3b.tar.gz | |
zephyr: enable power sequencing for kohaku
This adds gpio definitions and enables power sequencing for kohaku.
Right now power sequencing makes it to S0 and we start getting some
port 80 writes, but we fail at some point after then with some host
command errors. They look to be similar to some of the issues volteer
is having.
See log here if interested:
https://paste.googleplex.com/6055863094607872
So submitting this as good incremental progress, even if we can't get
AP fully booted yet.
BUG=b:177609422
BRANCH=none
TEST=on kohaku, make it to S0 with host command errors (see above)
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I9dbdd9837a2c4864b341b45626e4a1d5da101d8d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2633822
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'zephyr/projects/kohaku/include/gpio_map.h')
| -rw-r--r-- | zephyr/projects/kohaku/include/gpio_map.h | 38 |
1 files changed, 37 insertions, 1 deletions
diff --git a/zephyr/projects/kohaku/include/gpio_map.h b/zephyr/projects/kohaku/include/gpio_map.h index 3f5b436562..0552aa8994 100644 --- a/zephyr/projects/kohaku/include/gpio_map.h +++ b/zephyr/projects/kohaku/include/gpio_map.h @@ -9,7 +9,27 @@ #include <devicetree.h> #include <gpio_signal.h> +#define GPIO_AC_PRESENT NAMED_GPIO(acok_od) +#define GPIO_CPU_PROCHOT NAMED_GPIO(ec_prochot_odl) #define GPIO_EC_PCH_WAKE_ODL NAMED_GPIO(pch_wake_l) +#define GPIO_EN_A_RAILS NAMED_GPIO(en_a_rails) +#define GPIO_EN_PP5000_A NAMED_GPIO(en_pp5000_a) +#define GPIO_EN_PP5000 NAMED_GPIO(en_pp5000_a) +#define GPIO_LID_OPEN NAMED_GPIO(lid_open) +#define GPIO_PCH_PWRBTN_L NAMED_GPIO(pch_pwrbtn_l) +#define GPIO_PCH_RSMRST_L NAMED_GPIO(ec_pch_rsmrst_l) +#define GPIO_PCH_SLP_S0_L NAMED_GPIO(slp_s0_l) +#define GPIO_PCH_SLP_S3_L NAMED_GPIO(slp_s3_l) +#define GPIO_PCH_SLP_S4_L NAMED_GPIO(slp_s4_l) +#define GPIO_PCH_SYS_PWROK NAMED_GPIO(ec_pch_sys_pwrok) +#define GPIO_PG_EC_ALL_SYS_PWRGD NAMED_GPIO(pg_ec_all_sys_pwrgd) +#define GPIO_POWER_BUTTON_L NAMED_GPIO(power_button_l) +#define GPIO_PP5000_A_PG_OD NAMED_GPIO(pp5000_a_pg_od) +#define GPIO_RSMRST_L_PGOOD NAMED_GPIO(pg_ec_rsmrst_l) +#define GPIO_SYS_RESET_L NAMED_GPIO(sys_reset_l) + +/* Cometlake power sequencing requires this definition */ +#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD) /* * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items. @@ -26,6 +46,22 @@ * #define EC_CROS_GPIO_INTERRUPTS \ * GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print) */ -#define EC_CROS_GPIO_INTERRUPTS +#define EC_CROS_GPIO_INTERRUPTS \ + GPIO_INT(NAMED_GPIO(lid_open), GPIO_INT_EDGE_BOTH, lid_interrupt) \ + GPIO_INT(NAMED_GPIO(power_button_l), GPIO_INT_EDGE_BOTH, \ + power_button_interrupt) \ + GPIO_INT(NAMED_GPIO(acok_od), GPIO_INT_EDGE_BOTH, extpower_interrupt) \ + GPIO_INT(NAMED_GPIO(slp_s0_l), GPIO_INT_EDGE_BOTH, \ + power_signal_interrupt) \ + GPIO_INT(NAMED_GPIO(slp_s3_l), GPIO_INT_EDGE_BOTH, \ + power_signal_interrupt) \ + GPIO_INT(NAMED_GPIO(slp_s4_l), GPIO_INT_EDGE_BOTH, \ + power_signal_interrupt) \ + GPIO_INT(NAMED_GPIO(pg_ec_rsmrst_l), GPIO_INT_EDGE_BOTH, \ + intel_x86_rsmrst_signal_interrupt) \ + GPIO_INT(NAMED_GPIO(pg_ec_all_sys_pwrgd), GPIO_INT_EDGE_BOTH, \ + power_signal_interrupt) \ + GPIO_INT(NAMED_GPIO(pp5000_a_pg_od), GPIO_INT_EDGE_BOTH, \ + power_signal_interrupt) #endif /* __ZEPHYR_GPIO_MAP_H */ |