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| author | Wealian Liao <whliao@nuvoton.corp-partner.google.com> | 2021-05-03 18:34:31 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-05-19 19:29:49 +0000 |
| commit | 31dc11d5778645e974ebd1e75123c465ca411609 (patch) | |
| tree | ae583d1137e4cbe1d297f5a107d4327b7c1cb87d /zephyr/projects/kohaku | |
| parent | e19a8e92bcf167385f46270b486ff2179ed891f4 (diff) | |
| download | chrome-ec-31dc11d5778645e974ebd1e75123c465ca411609.tar.gz | |
zephyr: npcx: Move ecst configuration options to upstream
NPCX series ROM code changes the chip basic setting by firmware binary
header for loading the firmware from flash to RAM. All the NPCX series
chips could use it, so those configuration options are moved to
upstream.
The ecst chip version automatic select by CONFIG_SOC_NPCX7MNX.
Currently, the project setting doesn't set to the expected chip part
number. Change the following project to select the target chip &
configure ecst header:
- volteer: npcx7m7fc
- trogdor: npcx7m6fc
- kohaku: npcx7m6fc
BUG=b:184448653
BRANCH=none
TEST=zmake testall
TEST=volteer boot to OS
Cq-Depend: chromium:2872415
Signed-off-by: Yuval Peress <peress@chromium.org>
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Ieed6c21536401f70950ddd1f18d243b127d896ed
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2867128
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Tested-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'zephyr/projects/kohaku')
4 files changed, 9 insertions, 13 deletions
diff --git a/zephyr/projects/kohaku/boards/arm/kohaku/Kconfig.board b/zephyr/projects/kohaku/boards/arm/kohaku/Kconfig.board index 43cffd68e4..c1a1718847 100644 --- a/zephyr/projects/kohaku/boards/arm/kohaku/Kconfig.board +++ b/zephyr/projects/kohaku/boards/arm/kohaku/Kconfig.board @@ -4,7 +4,7 @@ config BOARD_KOHAKU bool "Google Kohaku EC" - depends on SOC_NPCX7M6FB # Actually NPCX7M6FC; C has 512K Flash + depends on SOC_NPCX7M6FC # NPCX doesn't actually have enough ram for coverage, but this will # allow generating initial 0 line coverage. select HAS_COVERAGE_SUPPORT diff --git a/zephyr/projects/kohaku/boards/arm/kohaku/board.cmake b/zephyr/projects/kohaku/boards/arm/kohaku/board.cmake index 3ce47418ca..fd6fcd0656 100644 --- a/zephyr/projects/kohaku/boards/arm/kohaku/board.cmake +++ b/zephyr/projects/kohaku/boards/arm/kohaku/board.cmake @@ -2,4 +2,4 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -set(ECST_CHIP_ARG npcx7m6) +set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.packed.bin) diff --git a/zephyr/projects/kohaku/boards/arm/kohaku/kohaku.dts b/zephyr/projects/kohaku/boards/arm/kohaku/kohaku.dts index 2ea08ec246..a2cbbde6c4 100644 --- a/zephyr/projects/kohaku/boards/arm/kohaku/kohaku.dts +++ b/zephyr/projects/kohaku/boards/arm/kohaku/kohaku.dts @@ -7,7 +7,7 @@ #include <cros/nuvoton/npcx.dtsi> #include <dt-bindings/gpio_defines.h> -#include <nuvoton/npcx7m6fb.dtsi> +#include <nuvoton/npcx7m6fc.dtsi> / { model = "Google Kohaku EC"; @@ -368,11 +368,6 @@ }; }; -/* Update flash size to 512KB from 196KB since we are using C variant */ -&flash0 { - reg = <0x10090000 0x80000>; -}; - &uart1 { status = "okay"; current-speed = <115200>; diff --git a/zephyr/projects/kohaku/boards/arm/kohaku/kohaku_defconfig b/zephyr/projects/kohaku/boards/arm/kohaku/kohaku_defconfig index 03ab175ef8..a92531faa1 100644 --- a/zephyr/projects/kohaku/boards/arm/kohaku/kohaku_defconfig +++ b/zephyr/projects/kohaku/boards/arm/kohaku/kohaku_defconfig @@ -6,13 +6,14 @@ CONFIG_SOC_SERIES_NPCX7=y # Platform Configuration -CONFIG_SOC_NPCX7M6FB=y # Actually NPCX7M6FC; C just has 512K Flash +CONFIG_SOC_NPCX7M6FC=y CONFIG_BOARD_KOHAKU=y -# NPCX BootLoader Table Configuration -CONFIG_PLATFORM_EC_RO_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2=y -CONFIG_PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_50=y -CONFIG_PLATFORM_EC_RO_HEADER_SPI_READ_MODE_DUAL=y +# Enable NPCX firmware header generator +CONFIG_NPCX_HEADER=y +CONFIG_NPCX_HEADER_SPI_MAX_CLOCK_50=y +CONFIG_NPCX_HEADER_SPI_READ_MODE_DUAL=y +CONFIG_NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2=y # Serial Drivers CONFIG_SERIAL=y |