Merge remote-tracking branch cros/main into firmware-keeby-14119.B-mainfirmware-keeby-14119.B-main

Relevant changes:

git log --oneline c5bd23a4b..b44d10f8f -- baseboard/dedede board/cappy2
board/corori board/driblee board/gooey board/haboki board/lalala
board/waddledoo2 common/charge_state_v2.c common/mkbp_* common/ocpc.c
common/usbc/usb_tc_drp_acc_trysrc_sm.c common/usbc/usb_sm.c
common/usbc/*_pd_* common/usbc/dp_alt_mode.c common/usbc/usb_prl_sm.c
common/usbc/usb_pe_drp_sm.c common/usb_charger.c common/usb_common.c
common/usbc_ocp.c driver/charger/sm5803.* driver/charger/isl923x.*
driver/tcpm/raa489000.* driver/tcpm/it83* include/power/icelake.h
include/intel_x86.h power/icelake.c power/intel_x86.c util/getversion.sh

42d03a001 config: change temp_sensor_power from config to gpio
e296efb28 usb_common: Fix CONFIG_USB_PD_DISCHARGE_TCPC typo
c346481f4 atomic: cast to unsigned when shifting
9b972a0f2 driver/tcpm/it83xx, it8xxx2: ITE inactive port return from HOOK
a499d8fd4 driver/tcpm/it83xx, it8xxx2: set sleep mask for mixed TCPC case
ed62e2583 TCPMv2: don't set the sleep mask for TCPC embedded in EC
c962696e8 motion_sensor: Remove |int_signal| field
86b216794 ocpc: modify pre-charge target condition
6f8336eb4 dedede: Set MKBP event wake mask to 0
02d034df0 dedede: add stylus fw_config
4f7cd7509 atomic: use atomic_t where it is possible
e3ffa0519 mkbp: change the type fifo_entries to atomic_t
bb4c47af0 usb: use atomic_t where possible
c6e513ee2 power/icelake: Add SLP_S5 as a watched power signal
d89e49b20 power: Introduce S4 as a real power state
ba8a3c9c0 chgstv2: Use chipset_in_state instead of naming states
23a975d12 i2c: Use declared initializers for i2c_ports: boards a-l
35865dbec TCPMv2: Guard DATA_RESET using CONFIG_USB_PD_DATA_RESET_MSG
d4d8243ed i2c: Use declared initializers for i2c_ports: baseboards
eba8d0305 RAA489000: Fixed RAA489000 max charging current
e78b83e0f TCPMv2: Delay Data Reset until mode entry request
6230e60fc TCPMv2: Support Data Reset as DFP, initiator
412246836 intel_x86: Apply chipset resume init and suspend complete hooks
f2809b72c config: rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPI

BRANCH=None
BUG=b:202796060 b:207805856 b:167983049 b:208318528 b:181983966
BUG=b:207328258 b:195416058 b:205285137 b:199919093 b:207055975
BUG=b:129159505 b:204947672 b:141363146 b:207082842 b:205675485
TEST=`make -j buildall`

Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I980351977e11088a130e478df0701be4715f049b

1 files changed, 110 insertions, 0 deletions

diff --git a/zephyr/projects/skyrim/power_signals.c b/zephyr/projects/skyrim/power_signals.c
new file mode 100644
index 0000000000..9f39edf505
--- /dev/null
+++ b/zephyr/projects/skyrim/power_signals.c
@@ -0,0 +1,110 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "config.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "power.h"
+#include "timer.h"
+
+/* Power Signal Input List */
+const struct power_signal_info power_signal_list[] = {
+	[X86_SLP_S3_N] = {
+		.gpio = GPIO_PCH_SLP_S3_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S3_DEASSERTED",
+	},
+	[X86_SLP_S5_N] = {
+		.gpio = GPIO_PCH_SLP_S5_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
+	[X86_S0_PGOOD] = {
+		.gpio = GPIO_S0_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S0_PGOOD",
+	},
+	[X86_S5_PGOOD] = {
+		.gpio = GPIO_S5_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S5_PGOOD",
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+static void baseboard_interrupt_init(void)
+{
+	/* Enable Power Group interrupts. */
+	gpio_enable_interrupt(GPIO_PG_GROUPC_S0_OD);
+	gpio_enable_interrupt(GPIO_PG_LPDDR5_S0_OD);
+	gpio_enable_interrupt(GPIO_PG_LPDDR5_S3_OD);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_interrupt_init, HOOK_PRIO_INIT_I2C + 1);
+
+/**
+ * b/175324615: On G3->S5, wait for RSMRST_L to be deasserted before asserting
+ * PCH_PWRBTN_L.
+ */
+void board_pwrbtn_to_pch(int level)
+{
+	timestamp_t start;
+	const uint32_t timeout_rsmrst_rise_us = 30 * MSEC;
+
+	/* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */
+	if (!level && !gpio_get_level(GPIO_PCH_RSMRST_L)) {
+		start = get_time();
+		do {
+			usleep(200);
+			if (gpio_get_level(GPIO_PCH_RSMRST_L))
+				break;
+		} while (time_since32(start) < timeout_rsmrst_rise_us);
+
+		if (!gpio_get_level(GPIO_PCH_RSMRST_L))
+			ccprints("Error pwrbtn: RSMRST_L still low");
+
+		msleep(16);
+	}
+	gpio_set_level(GPIO_PCH_PWRBTN_L, level);
+}
+
+/* Note: signal parameter unused */
+void baseboard_set_soc_pwr_pgood(enum gpio_signal unused)
+{
+	gpio_set_level(GPIO_EC_SOC_PWR_GOOD,
+				gpio_get_level(GPIO_EN_PWR_PCORE_S0_R) &&
+				gpio_get_level(GPIO_PG_LPDDR5_S0_OD));
+}
+
+/* Note: signal parameter unused */
+void baseboard_set_en_pwr_pcore(enum gpio_signal unused)
+{
+	/*
+	 * EC must AND signals PG_LPDDR5_S3_OD, PG_GROUPC_S0_OD, and
+	 * EN_PWR_S0_R
+	 */
+	gpio_set_level(GPIO_EN_PWR_PCORE_S0_R,
+					gpio_get_level(GPIO_PG_LPDDR5_S3_OD) &&
+					gpio_get_level(GPIO_PG_GROUPC_S0_OD) &&
+					gpio_get_level(GPIO_EN_PWR_S0_R));
+
+	/* Update EC_SOC_PWR_GOOD based on our results */
+	baseboard_set_soc_pwr_pgood(unused);
+}
+
+void baseboard_en_pwr_s0(enum gpio_signal signal)
+{
+
+	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
+	gpio_set_level(GPIO_EN_PWR_S0_R,
+		       gpio_get_level(GPIO_PCH_SLP_S3_L) &&
+		       gpio_get_level(GPIO_S5_PGOOD));
+
+	/* Change EN_PWR_PCORE_S0_R if needed*/
+	baseboard_set_en_pwr_pcore(signal);
+
+	/* Now chain off to the normal power signal interrupt handler. */
+	power_signal_interrupt(signal);
+}