Revert "Merge remote-tracking branch cros/main into factory-brya-14517.B-main"factory-brya-14517.B-main

This reverts commit af25602b15b22b9ef5821dcba9934311f2157c48.

Reason for revert: broken build due to ec-utils.

Original change's description:
> Merge remote-tracking branch cros/main into factory-brya-14517.B-main
>
> Generated by: util/update_release_branch.py --baseboard brya --relevant_paths_file
> baseboard/brya/relevant-paths.txt factory-brya-14517.B-main
>
> Relevant changes:
>
> git log --oneline 54462f034b..aa40b859b3 -- baseboard/brya board/agah
> board/anahera board/banshee board/brya board/crota board/felwinter
> board/gimble board/kano board/mithrax board/osiris board/primus
> board/redrix board/taeko board/taniks board/vell board/volmar
> driver/bc12/pi3usb9201_public.* driver/charger/bq25710.*
> driver/ppc/nx20p348x.* driver/ppc/syv682x_public.*
> driver/retimer/bb_retimer_public.* driver/tcpm/nct38xx.*
> driver/tcpm/ps8xxx_public.* driver/tcpm/tcpci.* include/power/alderlake*
> include/intel_x86.h power/alderlake* power/intel_x86.c
> util/getversion.sh
>
> e6da633c38 driver: Sort header files
> 234a87ae2d tcpci: Add FRS enable to driver structure
> a56be59ccd tcpm_header: add test for tcpm_dump_registers
> 57b3256963 Rename CONFIG_CHARGER_INPUT_CURRENT to _CHARGER_DEFAULT_CURRENT_LIMIT
> e420c8ff9a marasov: Modify TypeC and TypeA configuration.
> 43b53e0045 Add default implementation of board_set_charge_limit
> b75dc90677 Add CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT
> f1b563c350 baseboard: Sort header files
> 7d01b1e58d driver/retimer/ps8818.h: Add I2C ADDR FLAGS 0x30, 0x58, 0x70
> ec31407993 Add CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
> 8f89f69a5b crota: disable lid angle sensor for clamshell
>
> BRANCH=None
> BUG=b:259002141 b:255184961 b:247100970 b:259354679 b:260630630
> BUG=b:163093572 b:254328661
> TEST=`emerge-brya chromeos-ec`
>
> Force-Relevant-Builds: all
> Change-Id: Ia85a701fbf6b8e67ec214b9e25e0e55e980a6f47
> Signed-off-by: YH Lin <yueherngl@google.com>

Bug: b:259002141 b:255184961 b:247100970 b:259354679 b:260630630
Bug: b:163093572 b:254328661
Change-Id: I48d5aa4cc67a69ee1f6ac9255ac3087d34da4c72
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4077248
Tested-by: YH Lin <yueherngl@chromium.org>
Commit-Queue: YH Lin <yueherngl@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Auto-Submit: YH Lin <yueherngl@chromium.org>

1 files changed, 245 insertions, 0 deletions

diff --git a/zephyr/projects/skyrim/src/power_signals.c b/zephyr/projects/skyrim/src/power_signals.c
new file mode 100644
index 0000000000..5d372d35ae
--- /dev/null
+++ b/zephyr/projects/skyrim/src/power_signals.c
@@ -0,0 +1,245 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ap_power/ap_power.h"
+#include "charger.h"
+#include "chipset.h"
+#include "config.h"
+#include "gpio_signal.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "ioexpander.h"
+#include "power.h"
+#include "power/amd_x86.h"
+#include "timer.h"
+
+/* Power Signal Input List */
+/* TODO: b/218904113: Convert to using Zephyr GPIOs */
+const struct power_signal_info power_signal_list[] = {
+	[X86_SLP_S3_N] = {
+		.gpio = GPIO_PCH_SLP_S3_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S3_DEASSERTED",
+	},
+	[X86_SLP_S5_N] = {
+		.gpio = GPIO_PCH_SLP_S5_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
+	[X86_S0_PGOOD] = {
+		.gpio = GPIO_S0_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S0_PGOOD",
+	},
+	[X86_S5_PGOOD] = {
+		.gpio = GPIO_S5_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S5_PGOOD",
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/* Chipset hooks */
+static void baseboard_suspend_change(struct ap_power_ev_callback *cb,
+				     struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	default:
+		return;
+
+	case AP_POWER_SUSPEND:
+		/* Disable display backlight and retimer */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl),
+				1);
+		ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
+		break;
+
+	case AP_POWER_RESUME:
+		/* Enable retimer and display backlight */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl),
+				0);
+		ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
+		/* Any retimer tuning can be done after the retimer turns on */
+		break;
+	}
+}
+
+static void baseboard_init(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	/* Setup a suspend/resume callback */
+	ap_power_ev_init_callback(&cb, baseboard_suspend_change,
+				  AP_POWER_RESUME | AP_POWER_SUSPEND);
+	ap_power_ev_add_callback(&cb);
+	/* Enable Power Group interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s0));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s3));
+
+	/* Enable thermtrip interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_soc_thermtrip));
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_POST_I2C);
+
+/**
+ * b/227296844: On G3->S5, wait for RSMRST_L to be deasserted before asserting
+ * PCH_PWRBTN_L.  This can be as long as ~65ms after cold boot.  Then wait an
+ * additional delay of T1a defined in the EDS before changing the power button.
+ */
+#define RSMRST_WAIT_DELAY 70
+#define EDS_PWR_BTN_RSMRST_T1A_DELAY 16
+void board_pwrbtn_to_pch(int level)
+{
+	timestamp_t start;
+
+	/* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */
+	if (!level &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) {
+		start = get_time();
+		do {
+			usleep(500);
+			if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
+				    gpio_ec_soc_rsmrst_l)))
+				break;
+		} while (time_since32(start) < (RSMRST_WAIT_DELAY * MSEC));
+
+		if (!gpio_pin_get_dt(
+			    GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l)))
+			ccprints("Error pwrbtn: RSMRST_L still low");
+
+		msleep(EDS_PWR_BTN_RSMRST_T1A_DELAY);
+	}
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_btn_l), level);
+}
+
+/* Note: signal parameter unused */
+void baseboard_set_soc_pwr_pgood(enum gpio_signal unused)
+{
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_good),
+		gpio_pin_get_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s0_od)) &&
+			gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood)));
+}
+
+/* TODO(b/248284045): Remove when boards switch to new chip */
+#define MP2845A_I2C_ADDR_FLAGS 0x20
+#define MP2854A_MFR_VOUT_CMPS_MAX_REG 0x69
+#define MP2854A_MFR_LOW_PWR_SEL BIT(12)
+
+__overridable bool board_supports_pcore_ocp(void)
+{
+	return true;
+}
+
+static void setup_mp2845(void)
+{
+	if (i2c_update16(chg_chips[CHARGER_SOLO].i2c_port,
+			 MP2845A_I2C_ADDR_FLAGS, MP2854A_MFR_VOUT_CMPS_MAX_REG,
+			 MP2854A_MFR_LOW_PWR_SEL, MASK_CLR))
+		ccprints("Failed to send mp2845 workaround");
+
+	if (board_supports_pcore_ocp())
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_soc_pcore_ocp));
+}
+DECLARE_DEFERRED(setup_mp2845);
+
+void baseboard_s0_pgood(enum gpio_signal signal)
+{
+	baseboard_set_soc_pwr_pgood(signal);
+
+	/* Chain off power signal interrupt handler for PG_PCORE_S0_R_OD */
+	power_signal_interrupt(signal);
+
+	/* Set up the MP2845, which is powered in S0 */
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood)))
+		hook_call_deferred(&setup_mp2845_data, 50 * MSEC);
+	else
+		gpio_disable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_soc_pcore_ocp));
+}
+
+/* Note: signal parameter unused */
+void baseboard_set_en_pwr_pcore(enum gpio_signal unused)
+{
+	/*
+	 * EC must AND signals PG_LPDDR5_S3_OD, PG_GROUPC_S0_OD, and
+	 * EN_PWR_S0_R
+	 */
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r),
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r)));
+
+	/* Update EC_SOC_PWR_GOOD based on our results */
+	baseboard_set_soc_pwr_pgood(unused);
+}
+
+void baseboard_en_pwr_s0(enum gpio_signal signal)
+{
+	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r),
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5)));
+
+	/* Change EN_PWR_PCORE_S0_R if needed*/
+	baseboard_set_en_pwr_pcore(signal);
+
+	/* Now chain off to the normal power signal interrupt handler. */
+	power_signal_interrupt(signal);
+}
+#ifdef CONFIG_BOARD_USB_HUB_RESET
+void baseboard_enable_hub(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_rst), 0);
+}
+DECLARE_DEFERRED(baseboard_enable_hub);
+#endif /* CONFIG_BOARD_USB_HUB_RESET */
+
+void baseboard_s5_pgood(enum gpio_signal signal)
+{
+#ifdef CONFIG_BOARD_USB_HUB_RESET
+	/* We must enable the USB hub at least 30ms after S5 PGOOD */
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5)))
+		hook_call_deferred(&baseboard_enable_hub_data, 30 * MSEC);
+	else
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_rst), 1);
+#endif /* CONFIG_BOARD_USB_HUB_RESET */
+
+	/* Continue to our signal AND-ing and power interrupt */
+	baseboard_en_pwr_s0(signal);
+}
+
+void baseboard_set_en_pwr_s3(enum gpio_signal signal)
+{
+	/* EC must enable PWR_S3 when SLP_S5_L goes high, disable on low */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s3),
+			gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l)));
+
+	/* Chain off the normal power signal interrupt handler */
+	power_signal_interrupt(signal);
+}
+
+void baseboard_soc_thermtrip(enum gpio_signal signal)
+{
+	ccprints("SoC thermtrip reported, shutting down");
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
+}
+
+void baseboard_soc_pcore_ocp(enum gpio_signal signal)
+{
+	ccprints("SoC Pcore OCP reported, shutting down");
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM);
+}