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authorKeith Short <keithshort@chromium.org>2021-06-09 17:30:29 -0600
committerCommit Bot <commit-bot@chromium.org>2021-06-11 22:27:37 +0000
commit963cf28040860313986d5a0a842ba03d1b6ab215 (patch)
tree3db308c8f62bc6ae9b1a016a3ba8cc82b034177b /zephyr/projects/volteer
parent13f0d29b93b43dfdfece4ec2991c9869959778d3 (diff)
downloadchrome-ec-963cf28040860313986d5a0a842ba03d1b6ab215.tar.gz
zephyr: volteer: Delete configs set to NPCX defaults
Delete the Kconfig options that are now setup by default for the NPCX7 chipset. BUG=none BRANCH=none TEST=zmake testall TEST=boot zephyr on volteer Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I1e358964fac27aa15be849ce01357944d8fa906e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2954922 Reviewed-by: Yuval Peress <peress@chromium.org>
Diffstat (limited to 'zephyr/projects/volteer')
-rw-r--r--zephyr/projects/volteer/boards/arm/volteer/volteer_defconfig34
1 files changed, 0 insertions, 34 deletions
diff --git a/zephyr/projects/volteer/boards/arm/volteer/volteer_defconfig b/zephyr/projects/volteer/boards/arm/volteer/volteer_defconfig
index 0da58fbf16..478a74dde1 100644
--- a/zephyr/projects/volteer/boards/arm/volteer/volteer_defconfig
+++ b/zephyr/projects/volteer/boards/arm/volteer/volteer_defconfig
@@ -34,48 +34,14 @@ CONFIG_CLOCK_CONTROL=y
# WATCHDOG configuration
CONFIG_WATCHDOG=y
-# Set the delay time for printing panic data.
-# 1 cycle is about 32ms. 500ms is about 16 cycles.
-CONFIG_WDT_NPCX_DELAY_CYCLES=16
-
-# PLL configuration
-CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC=90000000
-CONFIG_CLOCK_NPCX_APB1_PRESCALER=6
-CONFIG_CLOCK_NPCX_APB2_PRESCALER=6
-CONFIG_CLOCK_NPCX_APB3_PRESCALER=6
-
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000
-
-# The following are valid for all:
-# Code RAM base for NPCX797FC
-CONFIG_CROS_EC_PROGRAM_MEMORY_BASE=0x10070000
-CONFIG_CROS_EC_RAM_BASE=0x200c0000
-CONFIG_CROS_EC_DATA_RAM_SIZE=0x00010000
-CONFIG_CROS_EC_RAM_SIZE=0x0000f800
-
-# Image size: MAX (1/2 Flash size, Code RAM size)
-# For NPCX796FC: Flash = 512 KiB, Code Ram 192 KiB
-# For NPCX797FC: Flash = 512 KiB, Code Ram 320 KiB
-CONFIG_CROS_EC_RO_MEM_OFF=0x0
-CONFIG_CROS_EC_RO_SIZE=0x40000
-# RW firmware in program memory - Identical to RO, only one image loaded at a
-# time.
-CONFIG_CROS_EC_RW_MEM_OFF=0x0
-CONFIG_CROS_EC_RW_SIZE=0x40000
-
-CONFIG_CROS_EC_HOOK_TICK_INTERVAL=200000
# ADC
# The resolution and oversamplig values are fixed by the NPCX ADC driver
CONFIG_ADC=y
CONFIG_ADC_SHELL=n
-CONFIG_PLATFORM_EC_ADC_RESOLUTION=10
-CONFIG_PLATFORM_EC_ADC_OVERSAMPLING=0
# Power Management
CONFIG_SOC_POWER_MANAGEMENT=y
CONFIG_PM_POLICY_APP=y
CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
CONFIG_SOC_POWER_MANAGEMENT_TRACE=y
-
-CONFIG_FLASH_SIZE=512