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| author | Ruibin Chang <Ruibin.Chang@ite.com.tw> | 2021-04-07 15:56:55 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-05-21 02:30:11 +0000 |
| commit | 2488b0595fca9f17cd31d61821512017d3536a0b (patch) | |
| tree | 1103262037301853dc1aef85cf9039b1ee1883c8 /zephyr/shim/chip/it8xxx2 | |
| parent | fb99538f460aa1265037bdca0ddaf0222c5860df (diff) | |
| download | chrome-ec-2488b0595fca9f17cd31d61821512017d3536a0b.tar.gz | |
zephyr: add clock to support it8xxx2 cros_kb_row driver
Add clock to support it8xxx2 cros_kb_row driver.
BUG=b:187192587
BRANCH=none
TEST=on hayato, read pll_reg_to_freq is same as setting.
Cq-Depend: chromium:2909732
Change-Id: I9fd9f6ca5c6796ad9aee22a5cf7dc23564d2a814
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2813880
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'zephyr/shim/chip/it8xxx2')
| -rw-r--r-- | zephyr/shim/chip/it8xxx2/CMakeLists.txt | 1 | ||||
| -rw-r--r-- | zephyr/shim/chip/it8xxx2/clock.c | 41 |
2 files changed, 42 insertions, 0 deletions
diff --git a/zephyr/shim/chip/it8xxx2/CMakeLists.txt b/zephyr/shim/chip/it8xxx2/CMakeLists.txt index f611a38958..7a92a3cfb6 100644 --- a/zephyr/shim/chip/it8xxx2/CMakeLists.txt +++ b/zephyr/shim/chip/it8xxx2/CMakeLists.txt @@ -4,6 +4,7 @@ zephyr_library_include_directories(include) +zephyr_library_sources(clock.c) zephyr_library_sources_ifdef(CONFIG_CROS_EC system.c) zephyr_library_sources_ifdef(CONFIG_CROS_EC pinmux.c) zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_ITE keyboard_raw.c) diff --git a/zephyr/shim/chip/it8xxx2/clock.c b/zephyr/shim/chip/it8xxx2/clock.c new file mode 100644 index 0000000000..2bcf9e2899 --- /dev/null +++ b/zephyr/shim/chip/it8xxx2/clock.c @@ -0,0 +1,41 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <device.h> +#include <drivers/clock_control.h> +#include <kernel.h> +#include <logging/log.h> +#include <soc.h> +#include <zephyr.h> +#include <soc/ite_it8xxx2/reg_def_cros.h> +#include <sys/util.h> + +#include "module_id.h" + +LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR); + +#define ECPM_NODE DT_INST(0, ite_it8xxx2_ecpm) +#define HAL_ECPM_REG_BASE_ADDR \ + ((struct ecpm_reg *)DT_REG_ADDR_BY_IDX(ECPM_NODE, 0)) +#define PLLFREQ_MASK 0xf + +static const int pll_reg_to_freq[8] = { + MHZ(8), + MHZ(16), + MHZ(24), + MHZ(32), + MHZ(48), + MHZ(64), + MHZ(72), + MHZ(96) +}; + +int clock_get_freq(void) +{ + struct ecpm_reg *const ecpm_base = HAL_ECPM_REG_BASE_ADDR; + int reg_val = ecpm_base->ECPM_PLLFREQ & PLLFREQ_MASK; + + return pll_reg_to_freq[reg_val]; +} |