summaryrefslogtreecommitdiff
path: root/zephyr/shim/chip/npcx/clock.c
diff options
context:
space:
mode:
authorSimon Glass <sjg@chromium.org>2020-11-05 14:59:00 -0700
committerCommit Bot <commit-bot@chromium.org>2020-12-01 04:11:18 +0000
commita3412be19e5c4121ee65160f634bc16f4c6b6045 (patch)
tree9e9e4b489bb926e6d5504aec42d8c197a849c62b /zephyr/shim/chip/npcx/clock.c
parent80964208e12d90d42dc9cecea7138776a73c6bb7 (diff)
downloadchrome-ec-a3412be19e5c4121ee65160f634bc16f4c6b6045.tar.gz
zephyr: shim the keyboard scan
It shims the keyboard_scan task by introducing another keyboard_raw.c which calls down to the zephyr-chrome cros_kb_raw driver. BRANCH=none BUG=b:167405015 TEST=Build pass by zmake configure -B ./build projects/experimental/volteer. TEST=Check all the keys on volteer platform by "ksstate". Change-Id: Ic87f67c28779f7feafa350020a07ba87e3600ecd Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Signed-off-by: Mulin Chao <MLChao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2523839 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Diffstat (limited to 'zephyr/shim/chip/npcx/clock.c')
-rw-r--r--zephyr/shim/chip/npcx/clock.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/zephyr/shim/chip/npcx/clock.c b/zephyr/shim/chip/npcx/clock.c
new file mode 100644
index 0000000000..8321d5f6d3
--- /dev/null
+++ b/zephyr/shim/chip/npcx/clock.c
@@ -0,0 +1,31 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <device.h>
+#include <drivers/clock_control.h>
+#include <dt-bindings/clock/npcx_clock.h>
+#include <kernel.h>
+#include <logging/log.h>
+#include <soc.h>
+#include <zephyr.h>
+
+LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR);
+
+int clock_get_freq(void)
+{
+ const struct device *clk_dev = device_get_binding(NPCX_CLK_CTRL_NAME);
+ const struct npcx_clk_cfg clk_cfg = {
+ .bus = NPCX_CLOCK_BUS_CORE,
+ };
+ uint32_t rate;
+
+ if (clock_control_get_rate(clk_dev, (clock_control_subsys_t *)&clk_cfg,
+ &rate) != 0) {
+ LOG_ERR("Get %s clock rate error", clk_dev->name);
+ return -EIO;
+ }
+
+ return rate;
+}