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| author | Yuval Peress <peress@chromium.org> | 2021-06-03 00:13:27 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-06-06 05:44:05 +0000 |
| commit | 03831f38edf58dfe2bc50b37a73b696a00ec5fd6 (patch) | |
| tree | d12da3b2f9c839e318bcd2026d9b82c5ae21b4e4 /zephyr/shim/chip/npcx/include/system_chip.h | |
| parent | e3d0d94a559dff751a4b4dc28617170be4f05ac8 (diff) | |
| download | chrome-ec-03831f38edf58dfe2bc50b37a73b696a00ec5fd6.tar.gz | |
zephyr: npcx9: implement system_mpu_config
This function is taken from chip/npcx/ and is used for the flash
workaround.
BRANCH=none
BUG=b:188605676
TEST=build brya
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I70775523d180a602c08f7059f0fe003c05007edf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2936007
Diffstat (limited to 'zephyr/shim/chip/npcx/include/system_chip.h')
| -rw-r--r-- | zephyr/shim/chip/npcx/include/system_chip.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/zephyr/shim/chip/npcx/include/system_chip.h b/zephyr/shim/chip/npcx/include/system_chip.h index 5ed7f655a6..e2e9d5379d 100644 --- a/zephyr/shim/chip/npcx/include/system_chip.h +++ b/zephyr/shim/chip/npcx/include/system_chip.h @@ -6,6 +6,48 @@ #ifndef __CROS_EC_SYSTEM_CHIP_H_ #define __CROS_EC_SYSTEM_CHIP_H_ +/*****************************************************************************/ +/* Memory mapping */ +#define CONFIG_LPRAM_BASE 0x40001400 /* memory address of lpwr ram */ +#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ + +/******************************************************************************/ +/* Optional M4 Registers */ +#define CPU_MPU_CTRL REG32(0xE000ED94) +#define CPU_MPU_RNR REG32(0xE000ED98) +#define CPU_MPU_RBAR REG32(0xE000ED9C) +#define CPU_MPU_RASR REG32(0xE000EDA0) + +/* + * Region assignment. 7 as the highest, a higher index has a higher priority. + * For example, using 7 for .iram.text allows us to mark entire RAM XN except + * .iram.text, which is used for hibernation. + * Region assignment is currently wasteful and can be changed if more + * regions are needed in the future. For example, a second region may not + * be necessary for all types, and REGION_CODE_RAM / REGION_STORAGE can be + * made mutually exclusive. + */ +enum mpu_region { + REGION_DATA_RAM = 0, /* For internal data RAM */ + REGION_DATA_RAM2 = 1, /* Second region for unaligned size */ + REGION_CODE_RAM = 2, /* For internal code RAM */ + REGION_CODE_RAM2 = 3, /* Second region for unaligned size */ + REGION_STORAGE = 4, /* For mapped internal storage */ + REGION_STORAGE2 = 5, /* Second region for unaligned size */ + REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */ + REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */ + /* only for chips with MPU supporting 16 regions */ + REGION_UNCACHED_RAM = 8, /* For uncached data RAM */ + REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */ + REGION_ROLLBACK = 10, /* For rollback */ +}; + +/* + * Configure the specific memory addresses in the the MPU + * (Memory Protection Unit) for Nuvoton different chip series. + */ +void system_mpu_config(void); + /* The utilities and variables depend on npcx chip family */ #if defined(CONFIG_SOC_SERIES_NPCX5) || \ defined(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API) |