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author | Tim Lin <tim2.lin@ite.corp-partner.google.com> | 2021-06-02 15:40:01 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2021-06-23 01:52:46 +0000 |
commit | 41165549be19ddc085bffc7b7abb09bc20b7eac5 (patch) | |
tree | 6d03d795dd9597811affc192aa0b435aabb71c2d /zephyr/shim/chip/npcx/include | |
parent | 7504878299b553aafc283abf47962518269ea12c (diff) | |
download | chrome-ec-41165549be19ddc085bffc7b7abb09bc20b7eac5.tar.gz |
zephyr: enable related configs for flash driver on it8xxx2
These flash related configs have to be enabled for the flash driver
of it8xxx2.
This CL also distinguishes the flash configs into header file of
it8xxx2 and npcx.
BUG=b:187192628
BRANCH=none
TEST=zmake -lDEBUG configure -b -B zephyr/build_ite \
zephyr/projects/it8xxx2_evb
zmake -lDEBUG configure -b -B zephyr/build_volteer \
zephyr/projects/volteer/volteer
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Change-Id: Ic6a2e89a24676d6ac484a389c938ab0692971be0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2952280
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'zephyr/shim/chip/npcx/include')
-rw-r--r-- | zephyr/shim/chip/npcx/include/flash_chip.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/zephyr/shim/chip/npcx/include/flash_chip.h b/zephyr/shim/chip/npcx/include/flash_chip.h new file mode 100644 index 0000000000..c8b3426e69 --- /dev/null +++ b/zephyr/shim/chip/npcx/include/flash_chip.h @@ -0,0 +1,28 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_FLASH_CHIP_H +#define __CROS_EC_FLASH_CHIP_H + +#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ +#ifdef CONFIG_FLASH_SIZE +#define CONFIG_FLASH_SIZE_BYTES (CONFIG_FLASH_SIZE * 1024) +#else +#define CONFIG_FLASH_SIZE_BYTES 0x0 +#endif + +/* TODO(b:176490413): use DT_PROP(DT_INST(inst, DT_DRV_COMPAT), size) ? */ +#define CONFIG_MAPPED_STORAGE_BASE 0x64000000 +#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ +#define CONFIG_FLASH_ERASE_SIZE 0x10000 +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE + +/* RO image resides at start of protected region, right after header */ +#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE + +#define CONFIG_RW_STORAGE_OFF 0 + +#endif /* __CROS_EC_FLASH_CHIP_H */ |