zephyr: npcx: add reset cause check

The reset cause will influence the initialization flow. We define some
of initial flow of the reset cause for the following development.

This CL include the following:
1. Add check_reset_cause() which sets the system reset flag.
2. Add chip_bbram_status_check() to clear the error status & show the
error message.
3. Add CONFIG_BOARD_RESET_AFTER_POWER_ON feature.
4. Define the initialize flow for reset cause.

BRANCH=none
BUG=b:178101173
TEST=check the following reset cause by 'sysinfo'
1. power-up
2. reset-pin reset
3. soft by 'reboot' console command
4. watchdog by 'waitms 2000'

Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I515868d8cda4544fdbe782210b0108b4dda0d8cc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2731180
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>

1 files changed, 39 insertions, 39 deletions

diff --git a/zephyr/shim/chip/npcx/system.c b/zephyr/shim/chip/npcx/system.c
index d776733827..96fccfebca 100644
--- a/zephyr/shim/chip/npcx/system.c
+++ b/zephyr/shim/chip/npcx/system.c
@@ -4,10 +4,8 @@
  */
 
 #include <drivers/cros_bbram.h>
-#include <drivers/cros_system.h>
 #include <logging/log.h>
 
-#include "watchdog.h"
 #include "system.h"
 
 #define GET_BBRAM_OFFSET(node) \
@@ -16,7 +14,7 @@
 
 LOG_MODULE_REGISTER(shim_npcx_system, LOG_LEVEL_ERR);
 
-const struct device *bbram_dev;
+const static struct device *bbram_dev;
 
 void chip_save_reset_flags(uint32_t flags)
 {
@@ -44,51 +42,53 @@ uint32_t chip_read_reset_flags(void)
 	return flags;
 }
 
-void system_reset(int flags)
+void chip_bbram_status_check(void)
 {
-	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
-	int err;
-	uint32_t save_flags;
-
-	if (!sys_dev)
-		LOG_ERR("sys_dev get binding failed");
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable_all();
-
-	/*  Get flags to be saved in BBRAM */
-	system_encode_save_flags(flags, &save_flags);
-
-	/* Store flags to battery backed RAM. */
-	chip_save_reset_flags(save_flags);
-
-	/* If WAIT_EXT is set, then allow 10 seconds for external reset */
-	if (flags & SYSTEM_RESET_WAIT_EXT) {
-		int i;
-
-		/* Wait 10 seconds for external reset */
-		for (i = 0; i < 1000; i++) {
-			watchdog_reload();
-			udelay(10000);
-		}
+	if (!bbram_dev) {
+		LOG_DBG("bbram_dev doesn't binding");
+		return;
 	}
 
-	err = cros_system_soc_reset(sys_dev);
-
-	if (err < 0)
-		LOG_ERR("soc reset failed");
-
-	/* should never return */
-	while (1)
-		;
+	if (cros_bbram_get_ibbr(bbram_dev)) {
+		LOG_ERR("VBAT power drop!");
+		cros_bbram_reset_ibbr(bbram_dev);
+	}
+	if (cros_bbram_get_vsby(bbram_dev)) {
+		LOG_ERR("VSBY power drop!");
+		cros_bbram_reset_vsby(bbram_dev);
+	}
+	if (cros_bbram_get_vcc1(bbram_dev)) {
+		LOG_ERR("VCC1 power drop!");
+		cros_bbram_reset_vcc1(bbram_dev);
+	}
 }
 
 static int chip_system_init(const struct device *unused)
 {
 	ARG_UNUSED(unused);
 
+	/*
+	 * NPCX chip uses BBRAM to save the reset flag. Binding & check BBRAM
+	 * here.
+	 */
 	bbram_dev = device_get_binding(DT_LABEL(DT_NODELABEL(bbram)));
+	if (!bbram_dev) {
+		LOG_ERR("bbram_dev gets binding failed");
+		return -1;
+	}
+
+	/* check the BBRAM status */
+	chip_bbram_status_check();
+
 	return 0;
 }
-
-SYS_INIT(chip_system_init, PRE_KERNEL_1, 50);
+/*
+ * The priority should be lower than CROS_BBRAM_NPCX_INIT_PRIORITY.
+ */
+#if (CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY <= \
+     CONFIG_CROS_BBRAM_NPCX_INIT_PRIORITY)
+#error CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY must greater than \
+	CONFIG_CROS_BBRAM_NPCX_INIT_PRIORITY
+#endif
+SYS_INIT(chip_system_init, PRE_KERNEL_1,
+	 CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY);